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https://github.com/RPCS3/llvm-mirror.git
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[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output.
-amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs
-amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs
Differential Revision: https://reviews.llvm.org/D40091
llvm-svn: 320084
This commit is contained in:
Mark Searles
parent
33a8064970
commit
335078bea8
@ -54,6 +54,26 @@
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using namespace llvm;
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static cl::opt<unsigned> ForceZeroFlag(
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"amdgpu-waitcnt-forcezero",
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cl::desc("Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)"),
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cl::init(0), cl::Hidden);
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static cl::opt<unsigned> ForceExpFlag(
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"amdgpu-waitcnt-forceexp",
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cl::desc("Force emit a s_waitcnt expcnt(0) before the first <n> instrs"),
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cl::init(0), cl::Hidden);
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static cl::opt<unsigned> ForceLgkmFlag(
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"amdgpu-waitcnt-forcelgkm",
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cl::desc("Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs"),
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cl::init(0), cl::Hidden);
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static cl::opt<unsigned> ForceVmFlag(
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"amdgpu-waitcnt-forcevm",
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cl::desc("Force emit a s_waitcnt vmcnt(0) before the first <n> instrs"),
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cl::init(0), cl::Hidden);
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namespace {
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// Class of object that encapsulates latest instruction counter score
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@ -373,6 +393,10 @@ private:
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std::vector<std::unique_ptr<BlockWaitcntBrackets>> KillWaitBrackets;
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int32_t InstCnt = 0;
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bool ForceZero = false;
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int32_t ForceSwaitcnt[NUM_INST_CNTS];
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public:
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static char ID;
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@ -397,6 +421,14 @@ public:
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llvm::make_unique<BlockWaitcntBrackets>(*Bracket));
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}
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bool ForceEmit() const {
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for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS;
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T = (enum InstCounterType)(T + 1))
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if (ForceSwaitcnt[T] > 0)
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return true;
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return false;
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}
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bool mayAccessLDSThroughFlat(const MachineInstr &MI) const;
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MachineInstr *generateSWaitCntInstBefore(MachineInstr &MI,
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BlockWaitcntBrackets *ScoreBrackets);
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@ -1023,9 +1055,6 @@ MachineInstr *SIInsertWaitcnts::generateSWaitCntInstBefore(
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} // End of for loop that looks at all dest operands.
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}
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// TODO: Tie force zero to a compiler triage option.
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bool ForceZero = false;
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// Check to see if this is an S_BARRIER, and if an implicit S_WAITCNT 0
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// occurs before the instruction. Doing it here prevents any additional
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// S_WAITCNTs from being emitted if the instruction was marked as
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@ -1058,7 +1087,7 @@ MachineInstr *SIInsertWaitcnts::generateSWaitCntInstBefore(
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}
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// Does this operand processing indicate s_wait counter update?
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if (EmitSwaitcnt) {
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if (EmitSwaitcnt || ForceEmit()) {
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int CntVal[NUM_INST_CNTS];
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bool UseDefaultWaitcntStrategy = true;
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@ -1099,7 +1128,7 @@ MachineInstr *SIInsertWaitcnts::generateSWaitCntInstBefore(
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}
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// If we are not waiting on any counter we can skip the wait altogether.
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if (EmitSwaitcnt != 0) {
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if (EmitSwaitcnt != 0 || ForceEmit()) {
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MachineInstr *OldWaitcnt = ScoreBrackets->getWaitcnt();
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int Imm = (!OldWaitcnt) ? 0 : OldWaitcnt->getOperand(0).getImm();
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if (!OldWaitcnt || (AMDGPU::decodeVmcnt(IV, Imm) !=
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@ -1135,11 +1164,31 @@ MachineInstr *SIInsertWaitcnts::generateSWaitCntInstBefore(
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CompilerGeneratedWaitcntSet.insert(SWaitInst);
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}
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if (!EmitSwaitcnt) {
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for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS;
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T = (enum InstCounterType)(T + 1)) {
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if (ForceSwaitcnt[T] > 0 ) {
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DEBUG(dbgs() << "ForceSwaitcnt[" << T << "]: "
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<< ForceSwaitcnt[T] << '\n';);
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}
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}
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}
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const MachineOperand &Op =
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MachineOperand::CreateImm(AMDGPU::encodeWaitcnt(
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IV, CntVal[VM_CNT], CntVal[EXP_CNT], CntVal[LGKM_CNT]));
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IV,
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(ForceSwaitcnt[VM_CNT] > 0) ? 0 : CntVal[VM_CNT],
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(ForceSwaitcnt[EXP_CNT] > 0) ? 0 : CntVal[EXP_CNT],
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(ForceSwaitcnt[LGKM_CNT] > 0) ? 0 : CntVal[LGKM_CNT]));
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SWaitInst->addOperand(MF, Op);
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if (!EmitSwaitcnt) {
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for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS;
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T = (enum InstCounterType)(T + 1)) {
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--ForceSwaitcnt[T];
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}
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}
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if (CntVal[EXP_CNT] == 0) {
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ScoreBrackets->setMixedExpTypes(false);
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}
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@ -1518,7 +1567,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
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BlockWaitcntBrackets *ScoreBrackets = BlockWaitcntBracketsMap[&Block].get();
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DEBUG({
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dbgs() << "Block" << Block.getNumber();
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dbgs() << "*** Block" << Block.getNumber() << " ***";
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ScoreBrackets->dump();
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});
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@ -1591,7 +1640,7 @@ void SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
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DEBUG({ SWaitInst->print(dbgs() << '\n'); });
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}
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DEBUG({
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Inst.print(dbgs());
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dbgs() << "Instr" << ++InstCnt << ": " << Inst;
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ScoreBrackets->dump();
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});
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@ -1696,6 +1745,11 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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AMDGPUASI = ST->getAMDGPUAS();
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ForceZero = ForceZeroFlag;
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ForceSwaitcnt[VM_CNT] = ForceVmFlag;
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ForceSwaitcnt[EXP_CNT] = ForceExpFlag;
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ForceSwaitcnt[LGKM_CNT] = ForceLgkmFlag;
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HardwareLimits.VmcntMax = AMDGPU::getVmcntBitMask(IV);
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HardwareLimits.ExpcntMax = AMDGPU::getExpcntBitMask(IV);
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HardwareLimits.LgkmcntMax = AMDGPU::getLgkmcntBitMask(IV);
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41
test/CodeGen/AMDGPU/waitcnt-debug.mir
Normal file
41
test/CodeGen/AMDGPU/waitcnt-debug.mir
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@ -0,0 +1,41 @@
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcelgkm=1 -o - %s | FileCheck -check-prefixes=GCN,LGKM %s
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forceexp=2 -o - %s | FileCheck -check-prefixes=GCN,EXP %s
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcevm=3 -o - %s | FileCheck -check-prefixes=GCN,VM %s
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# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 -amdgpu-waitcnt-forcevm=2 -o - %s | FileCheck -check-prefixes=GCN,ZERO %s
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# check that the waitcnt pass options that force insertion of waitcnt instructions are working as expected
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...
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# GCN-LABEL: name: waitcnt-debug
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# LGKM: S_WAITCNT 127
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# LGKM-NEXT: S_NOP 0
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# LGKM-NEXT: S_NOP 0
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# EXP: S_WAITCNT 3855
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# EXP-NEXT: S_NOP 0
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# EXP-NEXT: S_WAITCNT 3855
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# EXP-NEXT: S_NOP 0
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# VM: S_WAITCNT 3952
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# VM-NEXT: S_NOP 0
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# VM-NEXT: S_WAITCNT 3952
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# VM-NEXT: S_NOP 0
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# VM-NEXT: S_WAITCNT 3952
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# VM-NEXT: S_NOP 0
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# ZERO: S_WAITCNT 0
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# ZERO-NEXT: S_WAITCNT 0
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# ZERO-NEXT: S_NOP 0
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# ZERO-NEXT: S_WAITCNT 0
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# ZERO-NEXT: S_NOP 0
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name: waitcnt-debug
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liveins:
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body: |
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bb.0:
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S_NOP 0
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S_NOP 0
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S_NOP 0
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S_NOP 0
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...
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