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[MSP430] Add missing instruction forms
* Add missing mm, [r|m]n, [r|m]p instruction forms. * Fix bit16mc instruction. Patch by Kristina Bessonova! Differential Revision: https://reviews.llvm.org/D56546 llvm-svn: 350902
This commit is contained in:
Anton Korobeynikov
parent
294c6aa6ef
commit
3372fe3874
@ -226,7 +226,6 @@ let isCodeGenOnly = 1, usesCustomInserter = 1 in {
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// Control Flow Instructions...
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//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def RET : IForm16<0b0100, DstReg, SrcPostInc, 2,
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(outs), (ins), "ret", [(MSP430retflag)]> {
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@ -292,6 +291,8 @@ let isCall = 1,
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def CALLm : II16m<0b101,
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(outs), (ins memsrc:$src),
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"call\t$src", [(MSP430call (load addr:$src))]>;
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def CALLn : II16n<0b101, (outs), (ins indreg:$rs), "call\t$rs", []>;
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def CALLp : II16p<0b101, (outs), (ins postreg:$rs), "call\t$rs", []>;
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}
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//===----------------------------------------------------------------------===//
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@ -315,7 +316,6 @@ def PUSH16i : II16i<0b100, (outs), (ins i16imm:$imm), "push\t$imm", []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions
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// FIXME: Provide proper encoding!
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let hasSideEffects = 0 in {
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def MOV8rr : I8rr<0b0100,
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(outs GR8:$rd), (ins GR8:$rs),
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@ -327,7 +327,6 @@ def MOV16rr : I16rr<0b0100,
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[]>;
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}
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// FIXME: Provide proper encoding!
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV8rc : I8rc<0b0100,
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(outs GR8:$rd), (ins cg8imm:$imm),
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@ -437,6 +436,11 @@ def MOV16mm : I16mm<0b0100,
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"mov\t{$src, $dst}",
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[(store (i16 (load addr:$src)), addr:$dst)]>;
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def MOV8mn : I8mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs),
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"mov.b\t{$rs, $dst}", []>;
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def MOV16mn : I16mn<0b0100, (outs), (ins memdst:$dst, indreg:$rs),
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"mov\t{$rs, $dst}", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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@ -619,11 +623,11 @@ def SETZ : InstAlias<"setz", (BIS16rc SR, 2)>;
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def : Pat<(MSP430rla GR8:$dst), (ADD8rr $dst, $dst)>;
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def : Pat<(MSP430rla GR16:$dst), (ADD16rr $dst, $dst)>;
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// Format-II (Single Operand) Instruction
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// Register mode
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let Constraints = "$rs = $rd" in {
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let Defs = [SR] in {
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// FIXME: memory variant!
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def RRA8r : II8r<0b010,
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(outs GR8:$rd), (ins GR8:$rs),
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"rra.b\t$rd",
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@ -646,9 +650,8 @@ def RRC16r : II16r<0b000,
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"rrc\t$rd",
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[(set GR16:$rd, (MSP430rrc GR16:$rs)),
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(implicit SR)]>;
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}
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} // Uses = [SR]
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// FIXME: Memory sext's ?
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def SEXT16r : II16r<0b011,
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(outs GR16:$rd), (ins GR16:$rs),
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"sxt\t$rd",
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@ -663,7 +666,6 @@ def ZEXT16r : I8rr<0b0100,
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"mov.b\t{$rs, $rd}",
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[(set GR16:$rd, (zext (trunc GR16:$rs)))]>;
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// FIXME: Memory bitswaps?
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def SWPB16r : II16r<0b001,
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(outs GR16:$rd), (ins GR16:$rs),
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"swpb\t$rd",
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@ -671,6 +673,61 @@ def SWPB16r : II16r<0b001,
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} // Constraints = "$src = $dst"
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// Indexed, indirect register and indirect autoincrement modes
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let Defs = [SR] in {
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def RRA8m : II8m<0b010,
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(outs), (ins memsrc:$src),
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"rra.b\t$src",
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[(store (MSP430rra (i8 (load addr:$src))), addr:$src),
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(implicit SR)]>;
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def RRA16m : II16m<0b010,
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(outs), (ins memsrc:$src),
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"rra\t$src",
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[(store (MSP430rra (i16 (load addr:$src))), addr:$src),
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(implicit SR)]>;
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def RRA8n : II8n<0b010, (outs), (ins indreg:$rs), "rra.b\t$rs", []>;
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def RRA16n : II16n<0b010, (outs), (ins indreg:$rs), "rra\t$rs", []>;
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def RRA8p : II8p<0b010, (outs), (ins postreg:$rs), "rra.b\t$rs", []>;
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def RRA16p : II16p<0b010, (outs), (ins postreg:$rs), "rra\t$rs", []>;
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let Uses = [SR] in {
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def RRC8m : II8m<0b000,
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(outs), (ins memsrc:$src),
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"rrc.b\t$src",
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[(store (MSP430rrc (i8 (load addr:$src))), addr:$src),
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(implicit SR)]>;
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def RRC16m : II16m<0b000,
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(outs), (ins memsrc:$src),
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"rrc\t$src",
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[(store (MSP430rrc (i16 (load addr:$src))), addr:$src),
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(implicit SR)]>;
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def RRC8n : II8n<0b000, (outs), (ins indreg:$rs), "rrc.b\t$rs", []>;
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def RRC16n : II16n<0b000, (outs), (ins indreg:$rs), "rrc\t$rs", []>;
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def RRC8p : II8p<0b000, (outs), (ins postreg:$rs), "rrc.b\t$rs", []>;
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def RRC16p : II16p<0b000, (outs), (ins postreg:$rs), "rrc\t$rs", []>;
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} // Uses = [SR]
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def SEXT16m : II16m<0b011,
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(outs), (ins memsrc:$src),
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"sxt\t$src",
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[(store (sext_inreg (extloadi16i8 addr:$src), i8),
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addr:$src),
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(implicit SR)]>;
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def SEXT16n : II16n<0b011, (outs), (ins indreg:$rs), "sxt\t$rs", []>;
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def SEXT16p : II16p<0b011, (outs), (ins postreg:$rs), "sxt\t$rs", []>;
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} // Defs = [SR]
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def SWPB16m : II16m<0b001,
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(outs), (ins memsrc:$src),
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"swpb\t$src",
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[(store (bswap (i16 (load addr:$src))), addr:$src)]>;
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def SWPB16n : II16n<0b001, (outs), (ins indreg:$rs), "swpb\t$rs", []>;
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def SWPB16p : II16p<0b001, (outs), (ins postreg:$rs), "swpb\t$rs", []>;
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// Integer comparisons
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let Defs = [SR] in {
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def CMP8rr : I8rr<0b1001,
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@ -733,6 +790,16 @@ def CMP16rm : I16rm<0b1001,
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[(MSP430cmp GR16:$rd, (load addr:$src)),
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(implicit SR)]>;
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def CMP8rn : I8rn<0b1001,
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(outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>;
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def CMP16rn : I16rn<0b1001,
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(outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>;
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def CMP8rp : I8rp<0b1001,
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(outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>;
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def CMP16rp : I16rp<0b1001,
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(outs), (ins GR16:$rd, postreg:$rs), "cmp\t$rs, $rd", []>;
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def CMP8mr : I8mr<0b1001,
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(outs), (ins memsrc:$dst, GR8:$rs),
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"cmp.b\t$rs, $dst",
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@ -743,6 +810,25 @@ def CMP16mr : I16mr<0b1001,
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"cmp\t$rs, $dst",
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[(MSP430cmp (load addr:$dst), GR16:$rs),
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(implicit SR)]>;
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def CMP8mm : I8mm<0b1001,
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(outs), (ins memdst:$dst, memsrc:$src),
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"cmp.b\t$src, $dst",
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[(MSP430cmp (load addr:$dst), (i8 (load addr:$src))),
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(implicit SR)]>;
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def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src),
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"cmp\t$src, $dst",
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[(MSP430cmp (load addr:$dst), (i16 (load addr:$src))),
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(implicit SR)]>;
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def CMP8mn : I8mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
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"cmp.b\t$rs, $dst", []>;
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def CMP16mn : I16mn<0b1001, (outs), (ins memsrc:$dst, indreg:$rs),
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"cmp\t$rs, $dst", []>;
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def CMP8mp : I8mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs),
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"cmp.b\t$rs, $dst", []>;
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def CMP16mp : I16mp<0b1001, (outs), (ins memsrc:$dst, postreg:$rs),
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"cmp\t$rs, $dst", []>;
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// BIT TESTS, just sets condition codes
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// Note that the C condition is set differently than when using CMP.
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@ -791,6 +877,16 @@ def BIT16rm : I16rm<0b1011,
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[(MSP430cmp (and_su GR16:$rd, (load addr:$src)), 0),
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(implicit SR)]>;
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def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
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"bit.b\t$rs, $rd", []>;
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def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),
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"bit\t$rs, $rd", []>;
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def BIT8rp : I8rp<0b1011, (outs), (ins GR8:$rd, postreg:$rs),
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"bit.b\t$rs, $rd", []>;
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def BIT16rp : I16rp<0b1011, (outs), (ins GR16:$rd, postreg:$rs),
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"bit\t$rs, $rd", []>;
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def BIT8mr : I8mr<0b1011,
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(outs), (ins memsrc:$dst, GR8:$rs),
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"bit.b\t$rs, $dst",
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@ -808,7 +904,7 @@ def BIT8mc : I8mc<0b1011,
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[(MSP430cmp (and_su (load addr:$dst), (i8 cg8imm:$imm)), 0),
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(implicit SR)]>;
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def BIT16mc : I16mc<0b1011,
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(outs), (ins memsrc:$dst, i16imm:$imm),
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(outs), (ins memdst:$dst, cg16imm:$imm),
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"bit\t$imm, $dst",
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[(MSP430cmp (and_su (load addr:$dst), (i16 cg16imm:$imm)), 0),
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(implicit SR)]>;
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@ -838,6 +934,16 @@ def BIT16mm : I16mm<0b1011,
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(load addr:$src)),
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0),
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(implicit SR)]>;
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def BIT8mn : I8mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
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"bit.b\t$rs, $dst", []>;
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def BIT16mn : I16mn<0b1011, (outs), (ins memsrc:$dst, indreg:$rs),
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"bit\t$rs, $dst", []>;
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def BIT8mp : I8mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs),
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"bit.b\t$rs, $dst", []>;
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def BIT16mp : I16mp<0b1011, (outs), (ins memsrc:$dst, postreg:$rs),
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"bit\t$rs, $dst", []>;
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} // Defs = [SR]
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def TST8r : InstAlias<"tst.b\t$dst", (CMP8rc GR8:$dst, 0)>;
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@ -67,3 +67,22 @@ entry:
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; CHECK-DAG: mov 2(r1), 6(r1)
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; CHECK-DAG: mov 0(r1), 4(r1)
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}
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define void @cmp(i16* %g, i16* %i) {
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entry:
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; CHECK-LABEL: cmp:
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; CHECK: cmp 8(r12), 4(r13)
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%add.ptr = getelementptr inbounds i16, i16* %g, i16 4
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%0 = load i16, i16* %add.ptr, align 2
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%add.ptr1 = getelementptr inbounds i16, i16* %i, i16 2
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%1 = load i16, i16* %add.ptr1, align 2
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%cmp = icmp sgt i16 %0, %1
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i16 0, i16* %g, align 2
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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@ -53,3 +53,21 @@ define void @xor() nounwind {
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ret void
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}
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define void @cmp(i8* %g, i8* %i) {
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entry:
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; CHECK-LABEL: cmp:
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; CHECK: cmp.b 4(r12), 2(r13)
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%add.ptr = getelementptr inbounds i8, i8* %g, i16 4
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%0 = load i8, i8* %add.ptr, align 1
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%add.ptr1 = getelementptr inbounds i8, i8* %i, i16 2
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%1 = load i8, i8* %add.ptr1, align 1
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%cmp = icmp sgt i8 %0, %1
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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store i8 0, i8* %g, align 2
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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68
test/CodeGen/MSP430/InstII.ll
Normal file
68
test/CodeGen/MSP430/InstII.ll
Normal file
@ -0,0 +1,68 @@
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; RUN: llc -march=msp430 < %s | FileCheck %s
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target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
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target triple = "msp430-generic-generic"
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define void @rra8m(i8* %i) {
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entry:
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; CHECK-LABEL: rra8m:
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; CHECK: rra.b 2(r12)
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%0 = getelementptr inbounds i8, i8* %i, i16 2
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%1 = load i8, i8* %0, align 1
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%shr = ashr i8 %1, 1
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store i8 %shr, i8* %0, align 1
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ret void
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}
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define void @rra16m(i16* %i) {
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entry:
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; CHECK-LABEL: rra16m:
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; CHECK: rra 4(r12)
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%0 = getelementptr inbounds i16, i16* %i, i16 2
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%1 = load i16, i16* %0, align 2
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%shr = ashr i16 %1, 1
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store i16 %shr, i16* %0, align 2
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ret void
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}
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; TODO: `clrc; rrc.b 2(r12)` is expected
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define void @rrc8m(i8* %g) {
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entry:
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; CHECK-LABEL: rrc8m:
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; CHECK: mov.b 2(r12), r13
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; CHECK: clrc
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; CHECK: rrc.b r13
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; CHECK: mov.b r13, 2(r12)
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%add.ptr = getelementptr inbounds i8, i8* %g, i16 2
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%0 = load i8, i8* %add.ptr, align 1
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%1 = lshr i8 %0, 1
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store i8 %1, i8* %add.ptr, align 1
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ret void
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}
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; TODO: `clrc; rrc 4(r12)` is expected
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define void @rrc16m(i16* %g) {
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entry:
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; CHECK-LABEL: rrc16m:
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; CHECK: mov 4(r12), r13
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; CHECK: clrc
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; CHECK: rrc r13
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; CHECK: mov r13, 4(r12)
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%add.ptr = getelementptr inbounds i16, i16* %g, i16 2
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%0 = load i16, i16* %add.ptr, align 2
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%shr = lshr i16 %0, 1
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store i16 %shr, i16* %add.ptr, align 2
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ret void
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}
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define void @sxt16m(i16* %x) {
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entry:
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; CHECK-LABEL: sxt16m:
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; CHECK: sxt 4(r12)
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%add.ptr = getelementptr inbounds i16, i16* %x, i16 2
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%0 = bitcast i16* %add.ptr to i8*
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%1 = load i8, i8* %0, align 1
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%conv = sext i8 %1 to i16
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store i16 %conv, i16* %add.ptr, align 2
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ret void
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}
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@ -19,9 +19,10 @@
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0x1f 0x40 0x2a 0x00 # CHECK: mov 42, r15
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0xb0 0x12 0x81 0x01 # CHECK: call #385
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0x97 0x12 0x06 0x00 # CHECK: call 6(r7)
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0xa7 0xb2 0x02 0x00 # CHECK: bit #34, 2(r7)
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0xa7 0xb2 0x02 0x00 # CHECK: bit #4, 2(r7)
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0xa9 0x57 0x08 0x00 # CHECK: add @r7, 8(r9)
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0xb7 0xe7 0xfe 0xff # CHECK: xor @r7+, -2(r7)
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0xbf 0x40 0x2a 0x00 0x0c 0x00 # CHECK: mov #42, 12(r15)
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0xb7 0xb0 0x22 0x00 0x02 0x00 # CHECK: bit #34, 2(r7)
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0x9a 0xb9 0x10 0x00 0x08 0x00 # CHECK: bit 16(r9), 8(r10)
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@ -93,6 +93,8 @@ foo:
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call r7
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call 6(r7)
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call @r7
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call @r7+
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call disp+6(r7)
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call &disp
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call disp
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@ -100,11 +102,61 @@ foo:
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; CHECK: call r7 ; encoding: [0x87,0x12]
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; CHECK: call 6(r7) ; encoding: [0x97,0x12,0x06,0x00]
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; CHECK: call @r7 ; encoding: [0xa7,0x12]
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; CHECK: call @r7+ ; encoding: [0xb7,0x12]
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; CHECK: call disp+6(r7) ; encoding: [0x97,0x12,A,A]
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; CHECK: call &disp ; encoding: [0x92,0x12,A,A]
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||||
; CHECK: call disp ; encoding: [0x90,0x12,A,A]
|
||||
; CHECK: call #disp ; encoding: [0xb0,0x12,A,A]
|
||||
|
||||
rra r7 ; CHECK: rra r7 ; encoding: [0x07,0x11]
|
||||
rra 2(r7) ; CHECK: rra 2(r7) ; encoding: [0x17,0x11,0x02,0x00]
|
||||
rra @r7 ; CHECK: rra @r7 ; encoding: [0x27,0x11]
|
||||
rra @r7+ ; CHECK: rra @r7+ ; encoding: [0x37,0x11]
|
||||
|
||||
rrc r7 ; CHECK: rrc r7 ; encoding: [0x07,0x10]
|
||||
rrc 2(r7) ; CHECK: rrc 2(r7) ; encoding: [0x17,0x10,0x02,0x00]
|
||||
rrc @r7 ; CHECK: rrc @r7 ; encoding: [0x27,0x10]
|
||||
rrc @r7+ ; CHECK: rrc @r7+ ; encoding: [0x37,0x10]
|
||||
|
||||
swpb r7 ; CHECK: swpb r7 ; encoding: [0x87,0x10]
|
||||
swpb 2(r7) ; CHECK: swpb 2(r7) ; encoding: [0x97,0x10,0x02,0x00]
|
||||
swpb @r7 ; CHECK: swpb @r7 ; encoding: [0xa7,0x10]
|
||||
swpb @r7+ ; CHECK: swpb @r7+ ; encoding: [0xb7,0x10]
|
||||
|
||||
sxt r7 ; CHECK: sxt r7 ; encoding: [0x87,0x11]
|
||||
sxt 2(r7) ; CHECK: sxt 2(r7) ; encoding: [0x97,0x11,0x02,0x00]
|
||||
sxt @r7 ; CHECK: sxt @r7 ; encoding: [0xa7,0x11]
|
||||
sxt @r7+ ; CHECK: sxt @r7+ ; encoding: [0xb7,0x11]
|
||||
|
||||
cmp r5, r7 ; CHECK: cmp r5, r7 ; encoding: [0x07,0x95]
|
||||
cmp 2(r5), r7 ; CHECK: cmp 2(r5), r7 ; encoding: [0x17,0x95,0x02,0x00]
|
||||
cmp #-1, r7 ; CHECK: cmp #-1, r7 ; encoding: [0x37,0x93]
|
||||
cmp #42, r7 ; CHECK: cmp #42, r7 ; encoding: [0x37,0x90,0x2a,0x00]
|
||||
cmp @r5, r7 ; CHECK: cmp @r5, r7 ; encoding: [0x27,0x95]
|
||||
cmp @r5+, r7 ; CHECK: cmp @r5+, r7 ; encoding: [0x37,0x95]
|
||||
|
||||
cmp r5, 2(r7) ; CHECK: cmp r5, 2(r7) ; encoding: [0x87,0x95,0x02,0x00]
|
||||
cmp 2(r7), 2(r7) ; CHECK: cmp 2(r7), 2(r7) ; encoding: [0x97,0x97,0x02,0x00,0x02,0x00]
|
||||
cmp #-1, 2(r7) ; CHECK: cmp #-1, 2(r7) ; encoding: [0xb7,0x93,0x02,0x00]
|
||||
cmp #42, 2(r7) ; CHECK: cmp #42, 2(r7) ; encoding: [0xb7,0x90,0x2a,0x00,0x02,0x00]
|
||||
cmp @r5, 2(r7) ; CHECK: cmp @r5, 2(r7) ; encoding: [0xa7,0x95,0x02,0x00]
|
||||
cmp @r5+, 2(r7) ; CHECK: cmp @r5+, 2(r7) ; encoding: [0xb7,0x95,0x02,0x00]
|
||||
|
||||
bit r5, r7 ; CHECK: bit r5, r7 ; encoding: [0x07,0xb5]
|
||||
bit 2(r5), r7 ; CHECK: bit 2(r5), r7 ; encoding: [0x17,0xb5,0x02,0x00]
|
||||
bit #-1, r7 ; CHECK: bit #-1, r7 ; encoding: [0x37,0xb3]
|
||||
bit #42, r7 ; CHECK: bit #42, r7 ; encoding: [0x37,0xb0,0x2a,0x00]
|
||||
bit @r5, r7 ; CHECK: bit @r5, r7 ; encoding: [0x27,0xb5]
|
||||
bit @r5+, r7 ; CHECK: bit @r5+, r7 ; encoding: [0x37,0xb5]
|
||||
|
||||
bit r5, 2(r7) ; CHECK: bit r5, 2(r7) ; encoding: [0x87,0xb5,0x02,0x00]
|
||||
bit 2(r7), 2(r7) ; CHECK: bit 2(r7), 2(r7) ; encoding: [0x97,0xb7,0x02,0x00,0x02,0x00]
|
||||
bit #-1, 2(r7) ; CHECK: bit #-1, 2(r7) ; encoding: [0xb7,0xb3,0x02,0x00]
|
||||
bit #42, 2(r7) ; CHECK: bit #42, 2(r7) ; encoding: [0xb7,0xb0,0x2a,0x00,0x02,0x00]
|
||||
bit @r5, 2(r7) ; CHECK: bit @r5, 2(r7) ; encoding: [0xa7,0xb5,0x02,0x00]
|
||||
bit @r5+, 2(r7) ; CHECK: bit @r5+, 2(r7) ; encoding: [0xb7,0xb5,0x02,0x00]
|
||||
|
||||
disp:
|
||||
.word 0xcafe
|
||||
.word 0xbabe
|
||||
|
||||
@ -1,10 +1,13 @@
|
||||
; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s
|
||||
mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
|
||||
mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
|
||||
mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
|
||||
mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
|
||||
mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
|
||||
mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
|
||||
|
||||
push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
|
||||
push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
|
||||
mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42]
|
||||
mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42]
|
||||
mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43]
|
||||
mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43]
|
||||
mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43]
|
||||
mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43]
|
||||
|
||||
push #8 ; CHECK: push #8 ; encoding: [0x32,0x12]
|
||||
push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00]
|
||||
|
||||
bit #1, 0(r7) ; CHECK: bit #1, 0(r7) ; encoding: [0x97,0xb3,0x00,0x00]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user