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[ARM] VCVTT fpround instruction selection
Similar to the recent patch for fpext, this adds vcvtb and vcvtt with insert into vector instruction selection patterns for fptruncs. This helps clear up a lot of register shuffling that we would otherwise do. Differential Revision: https://reviews.llvm.org/D81637
This commit is contained in:
David Green
parent
3705e589ad
commit
33b3ee4e0a
@ -756,6 +756,12 @@ def : FP16Pat<(f16 (fpround SPR:$Sm)),
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(COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
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def : FP16Pat<(fp_to_f16 SPR:$a),
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(i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
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(v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2),
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(SSubReg_f16_reg imm:$lane)))>;
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def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
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(v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2),
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(SSubReg_f16_reg imm:$lane)))>;
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def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
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@ -772,10 +778,17 @@ def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))),
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def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
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/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>,
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[/* Intentionally left blank, see patterns below */]>,
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Requires<[HasFP16]>,
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Sched<[WriteFPCVT]>;
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def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
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(v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2),
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(SSubReg_f16_reg imm:$lane)))>;
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def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
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(v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2),
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(SSubReg_f16_reg imm:$lane)))>;
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def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
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(outs DPR:$Dd), (ins SPR:$Sm),
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NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
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@ -77,19 +77,15 @@ entry:
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define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_lane_f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s2, s2
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; CHECKHARD-NEXT: vmov r0, s2
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; CHECKHARD-NEXT: vmov.16 d0[3], r0
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; CHECKHARD-NEXT: vcvtt.f16.f32 s1, s2
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_lane_f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov s0, r2
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vmov r2, s0
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; CHECKSOFT-NEXT: vmov.16 d16[3], r2
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vmov s2, r2
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s1, s2
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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@ -100,21 +96,17 @@ entry:
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define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_1:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
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; CHECKHARD-NEXT: vmov r0, s4
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; CHECKHARD-NEXT: vmov.16 d0[1], r0
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; CHECKHARD-NEXT: vcvtt.f16.f32 s0, s4
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vldr s0, [sp]
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; CHECKSOFT-NEXT: vmov d17, r2, r3
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov r12, s0
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; CHECKSOFT-NEXT: vmov.16 d16[1], r12
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; CHECKSOFT-NEXT: vmov r2, r3, d17
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vldr s4, [sp]
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s0, s4
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; CHECKSOFT-NEXT: vmov r2, r3, d1
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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@ -125,21 +117,17 @@ entry:
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define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_7:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
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; CHECKHARD-NEXT: vmov r0, s4
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; CHECKHARD-NEXT: vmov.16 d1[3], r0
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; CHECKHARD-NEXT: vcvtt.f16.f32 s3, s4
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vldr s0, [sp]
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; CHECKSOFT-NEXT: vmov d17, r2, r3
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov r12, s0
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; CHECKSOFT-NEXT: vmov.16 d17[3], r12
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: vmov r2, r3, d17
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vldr s4, [sp]
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s3, s4
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: vmov r2, r3, d1
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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@ -968,8 +968,8 @@ entry:
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define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
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; CHECK-LABEL: frem_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: vmov q5, q0
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@ -979,76 +979,61 @@ define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
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; CHECK-NEXT: vcvtb.f32.f16 s0, s16
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r4, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s20
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s24, r0
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s16
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vmov.16 q6[0], r4
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s24, s24
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; CHECK-NEXT: vcvtt.f16.f32 s24, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s21
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; CHECK-NEXT: vmov.16 q6[1], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s17
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s25, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s21
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; CHECK-NEXT: vmov.16 q6[2], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s17
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f16.f32 s25, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s22
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; CHECK-NEXT: vmov.16 q6[3], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s18
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s26, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s22
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; CHECK-NEXT: vmov.16 q6[4], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s18
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f16.f32 s26, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s23
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; CHECK-NEXT: vmov.16 q6[5], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s19
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s27, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s23
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; CHECK-NEXT: vmov.16 q6[6], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s19
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: bl fmodf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov.16 q6[7], r0
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; CHECK-NEXT: vcvtt.f16.f32 s27, s0
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; CHECK-NEXT: vmov q0, q6
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: pop {r4, pc}
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%out = frem <8 x half> %in1, %in2
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ret <8 x half> %out
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@ -112,70 +112,55 @@ entry:
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define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
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; CHECK-LABEL: cos_float16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov q4, q0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r4, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s20, r0
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vmov.16 q5[0], r4
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s20, s20
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; CHECK-NEXT: vcvtt.f16.f32 s20, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s17
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; CHECK-NEXT: vmov.16 q5[1], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s21, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s17
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; CHECK-NEXT: vmov.16 q5[2], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f16.f32 s21, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s18
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; CHECK-NEXT: vmov.16 q5[3], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s22, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s18
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; CHECK-NEXT: vmov.16 q5[4], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtt.f16.f32 s22, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s19
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; CHECK-NEXT: vmov.16 q5[5], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vcvtb.f16.f32 s23, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s19
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; CHECK-NEXT: vmov.16 q5[6], r0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl cosf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov.16 q5[7], r0
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; CHECK-NEXT: vcvtt.f16.f32 s23, s0
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; CHECK-NEXT: vmov q0, q5
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: pop {r4, pc}
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
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ret <8 x half> %0
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@ -239,70 +224,55 @@ entry:
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define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
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; CHECK-LABEL: sin_float16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov q4, q0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bl sinf
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-NEXT: vmov r4, s0
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; CHECK-NEXT: vcvtt.f32.f16 s0, s16
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl sinf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -366,70 +336,55 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
|
||||
; CHECK-LABEL: exp_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vmov q4, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl expf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -493,70 +448,55 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
|
||||
; CHECK-LABEL: exp2_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vmov q4, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl exp2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -620,70 +560,55 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
|
||||
; CHECK-LABEL: log_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vmov q4, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl logf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -747,70 +672,55 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
|
||||
; CHECK-LABEL: log2_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vmov q4, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log2f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -874,70 +784,55 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
|
||||
; CHECK-LABEL: log10_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: vmov q4, q0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s20, r0
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q5[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s20, s20
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s20, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov.16 q5[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s21, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov.16 q5[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s22, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov.16 q5[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: bl log10f
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q5[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s23, s0
|
||||
; CHECK-NEXT: vmov q0, q5
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
|
||||
ret <8 x half> %0
|
||||
@ -1007,8 +902,8 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
|
||||
; CHECK-LABEL: pow_float16_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: vmov q5, q0
|
||||
@ -1018,76 +913,61 @@ define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %s
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r4, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s20
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov s24, r0
|
||||
; CHECK-NEXT: vmov r2, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s16
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: mov r0, r2
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vmov.16 q6[0], r4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s24, s24
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s24, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s21
|
||||
; CHECK-NEXT: vmov.16 q6[1], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s25, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s21
|
||||
; CHECK-NEXT: vmov.16 q6[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s17
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s25, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s22
|
||||
; CHECK-NEXT: vmov.16 q6[3], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s26, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s22
|
||||
; CHECK-NEXT: vmov.16 q6[4], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s18
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s26, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s23
|
||||
; CHECK-NEXT: vmov.16 q6[5], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s27, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s23
|
||||
; CHECK-NEXT: vmov.16 q6[6], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtt.f32.f16 s0, s19
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: bl powf
|
||||
; CHECK-NEXT: vmov s0, r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q6[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s27, s0
|
||||
; CHECK-NEXT: vmov q0, q6
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
|
||||
ret <8 x half> %0
|
||||
|
||||
@ -1225,23 +1225,15 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmov r2, s4
|
||||
; CHECK-LE-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
|
||||
; CHECK-LE-NEXT: vmov.16 q1[1], r2
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
|
||||
; CHECK-LE-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
@ -1314,25 +1306,18 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmov r2, s0
|
||||
; CHECK-BE-NEXT: vmov.16 q0[0], r1
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
|
||||
; CHECK-BE-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
|
||||
; CHECK-BE-NEXT: vmov.16 q0[2], r1
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vmov.16 q0[3], r1
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
@ -1349,7 +1334,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
@ -1413,23 +1397,15 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: sub sp, #4
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmov r2, s4
|
||||
; CHECK-LE-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
|
||||
; CHECK-LE-NEXT: vmov.16 q1[1], r2
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
|
||||
; CHECK-LE-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
@ -1502,25 +1478,18 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: .pad #4
|
||||
; CHECK-BE-NEXT: sub sp, #4
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmov r2, s0
|
||||
; CHECK-BE-NEXT: vmov.16 q0[0], r1
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
|
||||
; CHECK-BE-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
|
||||
; CHECK-BE-NEXT: vmov.16 q0[2], r1
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vmov.16 q0[3], r1
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
@ -1537,7 +1506,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
@ -1601,23 +1569,15 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-LE-NEXT: sub sp, #20
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s0, #0
|
||||
; CHECK-LE-NEXT: vmov r1, s4
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmov r2, s4
|
||||
; CHECK-LE-NEXT: vmov.16 q1[0], r1
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
|
||||
; CHECK-LE-NEXT: vmov.16 q1[1], r2
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
|
||||
; CHECK-LE-NEXT: vmov.16 q1[2], r1
|
||||
; CHECK-LE-NEXT: vmov r1, s8
|
||||
; CHECK-LE-NEXT: vmov.16 q1[3], r1
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
|
||||
; CHECK-LE-NEXT: mov.w r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-LE-NEXT: it gt
|
||||
; CHECK-LE-NEXT: movgt r1, #1
|
||||
; CHECK-LE-NEXT: cmp r1, #0
|
||||
; CHECK-LE-NEXT: vcmp.f32 s1, #0
|
||||
; CHECK-LE-NEXT: cset r1, ne
|
||||
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-LE-NEXT: and r1, r1, #1
|
||||
@ -1698,25 +1658,18 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: .pad #20
|
||||
; CHECK-BE-NEXT: sub sp, #20
|
||||
; CHECK-BE-NEXT: vrev64.32 q1, q0
|
||||
; CHECK-BE-NEXT: movs r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
|
||||
; CHECK-BE-NEXT: vcmp.f32 s4, #0
|
||||
; CHECK-BE-NEXT: vmov r1, s0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmov r2, s0
|
||||
; CHECK-BE-NEXT: vmov.16 q0[0], r1
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
|
||||
; CHECK-BE-NEXT: vmov.16 q0[1], r2
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
|
||||
; CHECK-BE-NEXT: vmov.16 q0[2], r1
|
||||
; CHECK-BE-NEXT: vmov r1, s8
|
||||
; CHECK-BE-NEXT: vmov.16 q0[3], r1
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: mov.w r1, #0
|
||||
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
|
||||
; CHECK-BE-NEXT: vcmp.f32 s5, #0
|
||||
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
|
||||
; CHECK-BE-NEXT: it gt
|
||||
; CHECK-BE-NEXT: movgt r1, #1
|
||||
; CHECK-BE-NEXT: cmp r1, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: cset r1, ne
|
||||
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
|
||||
; CHECK-BE-NEXT: and r1, r1, #1
|
||||
@ -1733,7 +1686,6 @@ define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float>
|
||||
; CHECK-BE-NEXT: and r3, r3, #1
|
||||
; CHECK-BE-NEXT: vcmp.f32 s7, #0
|
||||
; CHECK-BE-NEXT: rsb.w r3, r3, #0
|
||||
; CHECK-BE-NEXT: mov.w r2, #0
|
||||
; CHECK-BE-NEXT: bfi r1, r3, #1, #1
|
||||
; CHECK-BE-NEXT: mov.w r3, #0
|
||||
; CHECK-BE-NEXT: it gt
|
||||
|
||||
@ -38,17 +38,9 @@ define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {
|
||||
; CHECK-LABEL: fptrunc_4:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s4, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s4, s1
|
||||
; CHECK-NEXT: vmov r1, s4
|
||||
; CHECK-NEXT: vmov.16 q1[0], r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s8, s2
|
||||
; CHECK-NEXT: vmov.16 q1[1], r1
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s3
|
||||
; CHECK-NEXT: vmov.16 q1[2], r0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s4, s1
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s5, s2
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s5, s3
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -61,29 +53,13 @@ define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s8
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s0, s9
|
||||
; CHECK-NEXT: vmov r1, s0
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s12, s10
|
||||
; CHECK-NEXT: vmov.16 q0[1], r1
|
||||
; CHECK-NEXT: vmov r0, s12
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s8, s4
|
||||
; CHECK-NEXT: vmov.16 q0[3], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s8, s5
|
||||
; CHECK-NEXT: vmov.16 q0[4], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s8, s6
|
||||
; CHECK-NEXT: vmov.16 q0[5], r0
|
||||
; CHECK-NEXT: vmov r0, s8
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s4, s7
|
||||
; CHECK-NEXT: vmov.16 q0[6], r0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[7], r0
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s0, s9
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s1, s10
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s1, s11
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s2, s4
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s2, s5
|
||||
; CHECK-NEXT: vcvtb.f16.f32 s3, s6
|
||||
; CHECK-NEXT: vcvtt.f16.f32 s3, s7
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = fptrunc <8 x float> %src1 to <8 x half>
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user