mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-18 18:42:46 +02:00
GlobalISel: Support fewerElementsVector for icmp/fcmp
Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
This commit is contained in:
Matt Arsenault
parent
bf5709a51f
commit
33bad384fc
@ -122,6 +122,8 @@ private:
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LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult
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fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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@ -1284,6 +1284,73 @@ LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
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}
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if (NarrowTy.isVector())
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MIRBuilder.buildConcatVectors(DstReg, DstRegs);
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else
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MIRBuilder.buildBuildVector(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned Src0Reg = MI.getOperand(2).getReg();
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LLT DstTy = MRI.getType(DstReg);
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LLT SrcTy = MRI.getType(Src0Reg);
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unsigned NumParts;
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LLT NarrowTy0, NarrowTy1;
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if (TypeIdx == 0) {
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unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
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unsigned OldElts = DstTy.getNumElements();
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NarrowTy0 = NarrowTy;
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NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
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NarrowTy1 = NarrowTy.isVector() ?
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LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
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SrcTy.getElementType();
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} else {
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unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
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unsigned OldElts = SrcTy.getNumElements();
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NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
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NarrowTy.getNumElements();
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NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
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DstTy.getScalarSizeInBits());
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NarrowTy1 = NarrowTy;
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}
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// FIXME: Don't know how to handle the situation where the small vectors
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// aren't all the same size yet.
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if (NarrowTy1.isVector() &&
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NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
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return UnableToLegalize;
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CmpInst::Predicate Pred
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= static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
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extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
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extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
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for (unsigned I = 0; I < NumParts; ++I) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
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DstRegs.push_back(DstReg);
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if (MI.getOpcode() == TargetOpcode::G_ICMP)
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MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
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else {
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MachineInstr *NewCmp
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= MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
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NewCmp->setFlags(MI.getFlags());
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}
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}
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if (NarrowTy0.isVector())
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MIRBuilder.buildConcatVectors(DstReg, DstRegs);
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else
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MIRBuilder.buildBuildVector(DstReg, DstRegs);
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@ -1295,9 +1362,7 @@ LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
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LegalizerHelper::LegalizeResult
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LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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unsigned Opc = MI.getOpcode();
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@ -1384,8 +1449,15 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_ICMP:
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case TargetOpcode::G_FCMP:
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return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_STORE: {
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// FIXME: Don't know how to handle secondary types yet.
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if (TypeIdx != 0)
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return UnableToLegalize;
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bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
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unsigned ValReg = MI.getOperand(0).getReg();
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unsigned AddrReg = MI.getOperand(1).getReg();
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@ -160,10 +160,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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.scalarize(0)
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.clampScalar(0, S32, S64);
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setAction({G_FCMP, S1}, Legal);
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setAction({G_FCMP, 1, S32}, Legal);
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setAction({G_FCMP, 1, S64}, Legal);
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getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
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.legalFor({{S64, S32}, {S32, S16}, {S64, S16},
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{S32, S1}, {S64, S1}, {S16, S1},
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@ -192,8 +188,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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setAction({G_BLOCK_ADDR, CodePtr}, Legal);
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setAction({G_ICMP, S1}, Legal);
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setAction({G_ICMP, 1, S32}, Legal);
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getActionDefinitionsBuilder({G_ICMP, G_FCMP})
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.legalFor({{S1, S32}, {S1, S64}})
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.widenScalarToNextPow2(1)
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.clampScalar(1, S32, S64)
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.clampMaxNumElements(0, S1, 1)
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.clampMaxNumElements(1, S32, 1);
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setAction({G_CTLZ, S32}, Legal);
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setAction({G_CTLZ_ZERO_UNDEF, S32}, Legal);
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@ -1,27 +1,153 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_fcmp_f32
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name: test_fcmp_s32
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body: |
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bb.0:
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bb.0.entry:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fcmp_f32
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; CHECK-LABEL: name: test_fcmp_s32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[COPY]]
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; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
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; CHECK: $vgpr0 = COPY [[SELECT]](s32)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = COPY $vgpr0
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%2:_(s1) = G_FCMP floatpred(uge), %0, %1
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%2:_(s1) = G_FCMP floatpred(oeq), %0, %1
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%3:_(s32) = G_SELECT %2, %0, %1
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$vgpr0 = COPY %3
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...
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---
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name: test_fcmp_f64
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name: test_fcmp_s64
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body: |
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bb.0:
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fcmp_f64
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; CHECK-LABEL: name: test_fcmp_s64
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s64), [[COPY]]
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; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
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; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $vgpr0_vgpr1
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%2:_(s1) = G_FCMP floatpred(uge), %0, %1
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%2:_(s1) = G_FCMP floatpred(oeq), %0, %1
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%3:_(s64) = G_SELECT %2, %0, %1
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: test_fcmp_s16
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fcmp_s16
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
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; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16)
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[FPEXT]](s32), [[FPEXT1]]
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
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; CHECK: $vgpr0 = COPY [[COPY3]](s32)
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%0:_(s16) = G_CONSTANT i16 0
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%1:_(s32) = COPY $vgpr0
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%2:_(s16) = G_TRUNC %1
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%3:_(s1) = G_FCMP floatpred(oeq), %0, %2
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%4:_(s16) = G_SELECT %3, %0, %2
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%5:_(s32) = G_ANYEXT %4
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$vgpr0 = COPY %5
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...
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---
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name: test_fcmp_v2s32
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fcmp_v2s32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV]]
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; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1)
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; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s1>)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0
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%2:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%3:_(<2 x s1>) = G_FCMP floatpred(oeq), %1, %2
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S_NOP 0, implicit %3
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...
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---
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name: test_fcmp_v2s32_flags
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fcmp_v2s32_flags
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: %8:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]]
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; CHECK: %9:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s1>) = G_BUILD_VECTOR %8(s1), %9(s1)
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; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s1>)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0
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%2:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%3:_(<2 x s1>) = nnan G_FCMP floatpred(oeq), %1, %2
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S_NOP 0, implicit %3
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...
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---
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name: test_fcmp_v3s32
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1_vgpr2
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; CHECK-LABEL: name: test_fcmp_v3s32
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; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
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; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV]](s32), [[UV3]]
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; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV1]](s32), [[UV4]]
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; CHECK: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV2]](s32), [[UV5]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1), [[FCMP2]](s1)
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; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s1>)
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%0:_(<3 x s32>) = G_IMPLICIT_DEF
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%1:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
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%2:_(<3 x s1>) = G_FCMP floatpred(oeq), %0, %1
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S_NOP 0, implicit %2
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...
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---
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name: test_fcmp_v4s32
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: test_fcmp_v4s32
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; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load 16)
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
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; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV]](s32), [[UV4]]
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; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV1]](s32), [[UV5]]
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; CHECK: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV2]](s32), [[UV6]]
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; CHECK: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV3]](s32), [[UV7]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1), [[FCMP2]](s1), [[FCMP3]](s1)
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; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s1>)
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%0:_(p1) = G_IMPLICIT_DEF
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%1:_(<4 x s32>) = G_LOAD %0 :: (volatile load 16)
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%2:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%3:_(<4 x s1>) = G_FCMP floatpred(oeq) , %1, %2
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S_NOP 0, implicit %3
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...
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@ -2,11 +2,11 @@
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# RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_icmp
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name: test_icmp_s32
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body: |
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bb.0.entry:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_icmp
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; CHECK-LABEL: name: test_icmp_s32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
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@ -15,6 +15,152 @@ body: |
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = COPY $vgpr0
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s32) = G_SELECT %2(s1), %0(s32), %1(s32)
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%3:_(s32) = G_SELECT %2, %0, %1
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$vgpr0 = COPY %3
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...
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---
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name: test_icmp_s64
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body: |
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bb.0.entry:
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liveins: $vgpr0_vgpr1
|
||||
; CHECK-LABEL: name: test_icmp_s64
|
||||
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s64), [[COPY]]
|
||||
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
|
||||
; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
|
||||
%0:_(s64) = G_CONSTANT i64 0
|
||||
%1:_(s64) = COPY $vgpr0_vgpr1
|
||||
%2:_(s1) = G_ICMP intpred(ne), %0, %1
|
||||
%3:_(s64) = G_SELECT %2, %0, %1
|
||||
$vgpr0_vgpr1 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_icmp_s16
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: test_icmp_s16
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
|
||||
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
|
||||
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
|
||||
%0:_(s16) = G_CONSTANT i16 0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s16) = G_TRUNC %1
|
||||
%3:_(s1) = G_ICMP intpred(ne), %0, %2
|
||||
%4:_(s16) = G_SELECT %3, %0, %2
|
||||
%5:_(s32) = G_ANYEXT %4
|
||||
$vgpr0 = COPY %5
|
||||
...
|
||||
|
||||
---
|
||||
name: test_icmp_s8
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $vgpr0
|
||||
; CHECK-LABEL: name: test_icmp_s8
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
|
||||
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
|
||||
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
|
||||
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[COPY5]](s32)
|
||||
%0:_(s8) = G_CONSTANT i16 0
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s8) = G_TRUNC %1
|
||||
%3:_(s1) = G_ICMP intpred(ne), %0, %2
|
||||
%4:_(s8) = G_SELECT %3, %0, %2
|
||||
%5:_(s32) = G_ANYEXT %4
|
||||
$vgpr0 = COPY %5
|
||||
...
|
||||
|
||||
---
|
||||
name: test_icmp_v2s32
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $vgpr0_vgpr1
|
||||
; CHECK-LABEL: name: test_icmp_v2s32
|
||||
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[UV1]]
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s1>) = G_BUILD_VECTOR [[ICMP]](s1), [[ICMP1]](s1)
|
||||
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s1>)
|
||||
%0:_(s32) = G_CONSTANT i32 0
|
||||
%1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0
|
||||
%2:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
%3:_(<2 x s1>) = G_ICMP intpred(ne), %1, %2
|
||||
S_NOP 0, implicit %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_icmp_v3s32
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $vgpr0_vgpr1_vgpr2
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_v3s32
|
||||
; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>)
|
||||
; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV3]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV4]]
|
||||
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV5]]
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s1>) = G_BUILD_VECTOR [[ICMP]](s1), [[ICMP1]](s1), [[ICMP2]](s1)
|
||||
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s1>)
|
||||
%0:_(<3 x s32>) = G_IMPLICIT_DEF
|
||||
%1:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
||||
%2:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
|
||||
S_NOP 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_icmp_v4s32
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_v4s32
|
||||
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load 16)
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)
|
||||
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](s32), [[UV4]]
|
||||
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV5]]
|
||||
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV2]](s32), [[UV6]]
|
||||
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV3]](s32), [[UV7]]
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[ICMP]](s1), [[ICMP1]](s1), [[ICMP2]](s1), [[ICMP3]](s1)
|
||||
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s1>)
|
||||
%0:_(p1) = G_IMPLICIT_DEF
|
||||
%1:_(<4 x s32>) = G_LOAD %0 :: (volatile load 16)
|
||||
%2:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%3:_(<4 x s1>) = G_ICMP intpred(ne), %1, %2
|
||||
S_NOP 0, implicit %3
|
||||
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user