mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 02:52:53 +02:00
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
This commit is contained in:
Chris Lattner
parent
b05131d907
commit
33d0622cdc
@ -244,7 +244,7 @@ class Instruction {
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string DisableEncoding = "";
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/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
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bits<64> TSFlags = 0;
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bits<32> TSFlags = 0;
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}
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/// Predicates - These are extra conditionals which are turned into instruction
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@ -15,8 +15,6 @@
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#ifndef LLVM_TARGET_TARGETINSTRDESC_H
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#define LLVM_TARGET_TARGETINSTRDESC_H
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#include "llvm/System/DataTypes.h"
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namespace llvm {
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class TargetRegisterClass;
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@ -133,7 +131,7 @@ public:
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unsigned short SchedClass; // enum identifying instr sched class
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const char * Name; // Name of the instruction record in td file
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unsigned Flags; // Flags identifying machine instr class
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uint64_t TSFlags; // Target Specific Flag values
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unsigned TSFlags; // Target Specific Flag values
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"
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@ -56,7 +56,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineInstr *MI = MBBI;
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MachineFunction &MF = *MI->getParent()->getParent();
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uint64_t TSFlags = MI->getDesc().TSFlags;
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unsigned TSFlags = MI->getDesc().TSFlags;
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bool isPre = false;
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switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
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default: return NULL;
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@ -488,7 +488,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
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// Basic size info comes from the TSFlags field.
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const TargetInstrDesc &TID = MI->getDesc();
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uint64_t TSFlags = TID.TSFlags;
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unsigned TSFlags = TID.TSFlags;
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unsigned Opc = MI->getOpcode();
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switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
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@ -137,25 +137,25 @@ static inline void setSlice(uint32_t &Bits, unsigned From, unsigned To,
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/// Various utilities for checking the target specific flags.
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/// A unary data processing instruction doesn't have an Rn operand.
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static inline bool isUnaryDP(uint64_t TSFlags) {
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static inline bool isUnaryDP(unsigned TSFlags) {
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return (TSFlags & ARMII::UnaryDP);
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}
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/// This four-bit field describes the addressing mode used.
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/// See also ARMBaseInstrInfo.h.
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static inline unsigned getAddrMode(uint64_t TSFlags) {
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static inline unsigned getAddrMode(unsigned TSFlags) {
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return (TSFlags & ARMII::AddrModeMask);
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}
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/// {IndexModePre, IndexModePost}
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/// Only valid for load and store ops.
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/// See also ARMBaseInstrInfo.h.
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static inline unsigned getIndexMode(uint64_t TSFlags) {
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static inline unsigned getIndexMode(unsigned TSFlags) {
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return (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
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}
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/// Pre-/post-indexed operations define an extra $base_wb in the OutOperandList.
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static inline bool isPrePostLdSt(uint64_t TSFlags) {
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static inline bool isPrePostLdSt(unsigned TSFlags) {
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return (TSFlags & ARMII::IndexModeMask) != 0;
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}
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@ -78,7 +78,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
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isLoad = TID.mayLoad();
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isStore = TID.mayStore();
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uint64_t TSFlags = TID.TSFlags;
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unsigned TSFlags = TID.TSFlags;
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isFirst = TSFlags & PPCII::PPC970_First;
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isSingle = TSFlags & PPCII::PPC970_Single;
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@ -232,7 +232,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
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MachineInstr *MI = I;
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uint64_t Flags = MI->getDesc().TSFlags;
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unsigned Flags = MI->getDesc().TSFlags;
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unsigned FPInstClass = Flags & X86II::FPTypeMask;
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if (MI->isInlineAsm())
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@ -83,7 +83,6 @@ def SSEPackedInt : Domain<3>;
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class OpSize { bit hasOpSizePrefix = 1; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class VEX_4V { bit hasVEX_4VPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class SegFS { bits<2> SegOvrBits = 1; }
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class SegGS { bits<2> SegOvrBits = 2; }
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@ -125,7 +124,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
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bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV prefix?
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FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
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bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
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bits<2> SegOvrBits = 0; // Segment override prefix.
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@ -143,7 +141,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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let TSFlags{21-20} = SegOvrBits;
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let TSFlags{23-22} = ExeDomain.Value;
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let TSFlags{31-24} = Opcode;
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let TSFlags{32} = hasVEX_4VPrefix;
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}
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class I<bits<8> o, Format f, dag outs, dag ins, string asm,
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@ -219,7 +216,6 @@ class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
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// SSI - SSE1 instructions with XS prefix.
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// PSI - SSE1 instructions with TB prefix.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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// VSSI - SSE1 instructions with XS prefix in AVX form.
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class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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@ -233,10 +229,6 @@ class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
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Requires<[HasSSE1]>;
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class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS, VEX_4V,
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Requires<[HasAVX, HasSSE1]>;
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// SSE2 Instruction Templates:
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//
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@ -245,7 +237,6 @@ class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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// VSDI - SSE2 instructions with XD prefix in AVX form.
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class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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@ -262,10 +253,6 @@ class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
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Requires<[HasSSE2]>;
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class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD, VEX_4V,
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Requires<[HasAVX, HasSSE2]>;
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// SSE3 Instruction Templates:
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//
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@ -417,36 +417,22 @@ namespace X86II {
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OpcodeShift = 24,
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OpcodeMask = 0xFF << OpcodeShift
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};
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// FIXME: The enum opcode space is over and more bits are needed. Anywhere
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// those enums below are used, TSFlags must be shifted right by 32 first.
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enum {
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//===------------------------------------------------------------------===//
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// VEX_4V - VEX prefixes are instruction prefixes used in AVX.
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// VEX_4V is used to specify an additional AVX/SSE register. Several 2
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// address instructions in SSE are represented as 3 address ones in AVX
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// and the additional register is encoded in VEX_VVVV prefix.
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//
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VEXShift = 0,
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VEX_4V = 1 << VEXShift
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};
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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//
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static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
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static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) {
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return TSFlags >> X86II::OpcodeShift;
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}
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static inline bool hasImm(uint64_t TSFlags) {
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static inline bool hasImm(unsigned TSFlags) {
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return (TSFlags & X86II::ImmMask) != 0;
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}
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/// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
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/// of the specified instruction.
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static inline unsigned getSizeOfImm(uint64_t TSFlags) {
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static inline unsigned getSizeOfImm(unsigned TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8:
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@ -460,7 +446,7 @@ namespace X86II {
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/// isImmPCRel - Return true if the immediate of the specified instruction's
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/// TSFlags indicates that it is pc relative.
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static inline unsigned isImmPCRel(uint64_t TSFlags) {
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static inline unsigned isImmPCRel(unsigned TSFlags) {
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switch (TSFlags & X86II::ImmMask) {
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default: assert(0 && "Unknown immediate size");
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case X86II::Imm8PCRel:
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@ -673,26 +673,6 @@ multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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let isCommutable = Commutable;
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}
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def V#NAME#SSrr : VSSI<opc, MRMSrcReg, (outs FR32:$dst),
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(ins FR32:$src1, FR32:$src2),
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!strconcat(OpcodeStr,
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"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]> {
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let isCommutable = Commutable;
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let Constraints = "";
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let isAsmParserOnly = 1;
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}
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def V#NAME#SDrr : VSDI<opc, MRMSrcReg, (outs FR64:$dst),
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(ins FR64:$src1, FR64:$src2),
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!strconcat(OpcodeStr,
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"sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]> {
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let isCommutable = Commutable;
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let Constraints = "";
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let isAsmParserOnly = 1;
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}
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// Scalar operation, reg+mem.
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def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
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(ins FR32:$src1, f32mem:$src2),
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@ -101,19 +101,12 @@ public:
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void EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
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unsigned TSFlags, unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const;
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void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const;
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};
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} // end anonymous namespace
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@ -140,7 +133,7 @@ static bool isDisp8(int Value) {
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/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
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/// in an instruction with the specified TSFlags.
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static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
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static MCFixupKind getImmFixupKind(unsigned TSFlags) {
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unsigned Size = X86II::getSizeOfImm(TSFlags);
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bool isPCRel = X86II::isImmPCRel(TSFlags);
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@ -191,7 +184,7 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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uint64_t TSFlags, unsigned &CurByte,
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unsigned TSFlags, unsigned &CurByte,
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raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const{
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const MCOperand &Disp = MI.getOperand(Op+3);
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@ -331,159 +324,10 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
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}
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/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
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/// called VEX.
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void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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// Pseudo instructions never have a VEX prefix.
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if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
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return;
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// VEX_R: opcode externsion equivalent to REX.R in
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// 1's complement (inverted) form
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//
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// 1: Same as REX_R=0 (must be 1 in 32-bit mode)
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// 0: Same as REX_R=1 (64 bit mode only)
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//
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unsigned char VEX_R = 0x1;
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// VEX_B:
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//
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// 1: Same as REX_B=0 (ignored in 32-bit mode)
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// 0: Same as REX_B=1 (64 bit mode only)
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//
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unsigned char VEX_B = 0x1;
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// VEX_W: opcode specific (use like REX.W, or used for
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// opcode extension, or ignored, depending on the opcode byte)
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unsigned char VEX_W = 0;
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// VEX_5M (VEX m-mmmmm field):
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//
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// 0b00000: Reserved for future use
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// 0b00001: implied 0F leading opcode
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// 0b00010: implied 0F 38 leading opcode bytes
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// 0b00011: implied 0F 3A leading opcode bytes
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// 0b00100-0b11111: Reserved for future use
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//
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unsigned char VEX_5M = 0x1;
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// VEX_4V (VEX vvvv field): a register specifier
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// (in 1's complement form) or 1111 if unused.
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unsigned char VEX_4V = 0xf;
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// VEX_L (Vector Length):
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//
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// 0: scalar or 128-bit vector
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// 1: 256-bit vector
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//
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unsigned char VEX_L = 0;
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// VEX_PP: opcode extension providing equivalent
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// functionality of a SIMD prefix
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//
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// 0b00: None
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// 0b01: 66 (not handled yet)
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// 0b10: F3
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// 0b11: F2
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//
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unsigned char VEX_PP = 0;
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switch (TSFlags & X86II::Op0Mask) {
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default: assert(0 && "Invalid prefix!");
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case 0: break; // No prefix!
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case X86II::T8: // 0F 38
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VEX_5M = 0x2;
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break;
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case X86II::TA: // 0F 3A
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VEX_5M = 0x3;
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break;
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case X86II::TF: // F2 0F 38
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VEX_PP = 0x3;
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VEX_5M = 0x2;
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break;
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case X86II::XS: // F3 0F
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VEX_PP = 0x2;
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break;
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case X86II::XD: // F2 0F
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VEX_PP = 0x3;
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break;
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}
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unsigned NumOps = MI.getNumOperands();
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unsigned i = 0;
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unsigned SrcReg = 0, SrcRegNum = 0;
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
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case X86II::MRMSrcReg:
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if (MI.getOperand(0).isReg() &&
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X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
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VEX_R = 0x0;
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// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
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// range 0-7 and the difference between the 2 groups is given by the
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// REX prefix. In the VEX prefix, registers are seen sequencially
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// from 0-15 and encoded in 1's complement form, example:
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//
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// ModRM field => XMM9 => 1
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// VEX.VVVV => XMM9 => ~9
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//
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// See table 4-35 of Intel AVX Programming Reference for details.
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SrcReg = MI.getOperand(1).getReg();
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SrcRegNum = GetX86RegNum(MI.getOperand(1));
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if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
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SrcRegNum += 8;
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// The registers represented through VEX_VVVV should
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// be encoded in 1's complement form.
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if ((TSFlags >> 32) & X86II::VEX_4V)
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VEX_4V = (~SrcRegNum) & 0xf;
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i = 2; // Skip the VEX.VVVV operand.
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for (; i != NumOps; ++i) {
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const MCOperand &MO = MI.getOperand(i);
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if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
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VEX_B = 0x0;
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}
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||||
break;
|
||||
default:
|
||||
assert(0 && "Not implemented!");
|
||||
}
|
||||
|
||||
// VEX opcode prefix can have 2 or 3 bytes
|
||||
//
|
||||
// 3 bytes:
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// 2 bytes:
|
||||
// +-----+ +-------------------+
|
||||
// | C5h | | R | vvvv | L | pp |
|
||||
// +-----+ +-------------------+
|
||||
//
|
||||
// Note: VEX.X isn't used so far
|
||||
//
|
||||
unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
|
||||
|
||||
if (VEX_B /* & VEX_X */) { // 2 byte VEX prefix
|
||||
EmitByte(0xC5, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
|
||||
return;
|
||||
}
|
||||
|
||||
// 3 byte VEX prefix
|
||||
EmitByte(0xC4, CurByte, OS);
|
||||
EmitByte(VEX_R << 7 | 1 << 6 /* VEX_X = 1 */ | VEX_5M, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
|
||||
}
|
||||
|
||||
/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
|
||||
/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
|
||||
/// size, and 3) use of X86-64 extended registers.
|
||||
static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
|
||||
static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
|
||||
const TargetInstrDesc &Desc) {
|
||||
// Pseudo instructions never have a rex byte.
|
||||
if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
|
||||
@ -578,10 +422,18 @@ static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
|
||||
return REX;
|
||||
}
|
||||
|
||||
/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
|
||||
void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
const MCInst &MI, const TargetInstrDesc &Desc,
|
||||
raw_ostream &OS) const {
|
||||
void X86MCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
const TargetInstrDesc &Desc = TII.get(Opcode);
|
||||
unsigned TSFlags = Desc.TSFlags;
|
||||
|
||||
// Keep track of the current byte being emitted.
|
||||
unsigned CurByte = 0;
|
||||
|
||||
// FIXME: We should emit the prefixes in exactly the same order as GAS does,
|
||||
// in order to provide diffability.
|
||||
|
||||
// Emit the lock opcode prefix as needed.
|
||||
if (TSFlags & X86II::LOCK)
|
||||
@ -664,30 +516,6 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
EmitByte(0x3A, CurByte, OS);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void X86MCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
const TargetInstrDesc &Desc = TII.get(Opcode);
|
||||
uint64_t TSFlags = Desc.TSFlags;
|
||||
|
||||
// Keep track of the current byte being emitted.
|
||||
unsigned CurByte = 0;
|
||||
|
||||
// Is this instruction encoded in AVX form?
|
||||
bool IsAVXForm = false;
|
||||
if ((TSFlags >> 32) & X86II::VEX_4V)
|
||||
IsAVXForm = true;
|
||||
|
||||
// FIXME: We should emit the prefixes in exactly the same order as GAS does,
|
||||
// in order to provide diffability.
|
||||
|
||||
if (!IsAVXForm)
|
||||
EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
|
||||
else
|
||||
EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
|
||||
|
||||
// If this is a two-address instruction, skip one of the register operands.
|
||||
unsigned NumOps = Desc.getNumOperands();
|
||||
@ -699,7 +527,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
--NumOps;
|
||||
|
||||
unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
|
||||
unsigned SrcRegNum = 0;
|
||||
switch (TSFlags & X86II::FormMask) {
|
||||
case X86II::MRMInitReg:
|
||||
assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
|
||||
@ -731,14 +558,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
|
||||
case X86II::MRMSrcReg:
|
||||
EmitByte(BaseOpcode, CurByte, OS);
|
||||
SrcRegNum = CurOp + 1;
|
||||
|
||||
if (IsAVXForm) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
SrcRegNum++;
|
||||
|
||||
EmitRegModRMByte(MI.getOperand(SrcRegNum),
|
||||
GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
|
||||
CurOp = SrcRegNum + 1;
|
||||
EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
|
||||
CurByte, OS);
|
||||
CurOp += 2;
|
||||
break;
|
||||
|
||||
case X86II::MRMSrcMem: {
|
||||
|
||||
@ -10052,35 +10052,3 @@ pshufb CPI1_0(%rip), %xmm1
|
||||
// CHECK: ficomps 32493
|
||||
// CHECK: encoding: [0xde,0x1d,0xed,0x7e,0x00,0x00]
|
||||
ficomps 32493
|
||||
|
||||
// CHECK: vaddss %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xca,0x58,0xd4]
|
||||
vaddss %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vmulss %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xca,0x59,0xd4]
|
||||
vmulss %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vsubss %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xca,0x5c,0xd4]
|
||||
vsubss %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vdivss %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xca,0x5e,0xd4]
|
||||
vdivss %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vaddsd %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xcb,0x58,0xd4]
|
||||
vaddsd %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vmulsd %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xcb,0x59,0xd4]
|
||||
vmulsd %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vsubsd %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xcb,0x5c,0xd4]
|
||||
vsubsd %xmm4, %xmm6, %xmm2
|
||||
|
||||
// CHECK: vdivsd %xmm4, %xmm6, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xcb,0x5e,0xd4]
|
||||
vdivsd %xmm4, %xmm6, %xmm2
|
||||
|
||||
@ -103,35 +103,3 @@ movd %mm1, %rdx
|
||||
// CHECK: movd %mm1, %edx
|
||||
// CHECK: encoding: [0x0f,0x7e,0xca]
|
||||
movd %mm1, %edx
|
||||
|
||||
// CHECK: vaddss %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x32,0x58,0xd0]
|
||||
vaddss %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vmulss %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x32,0x59,0xd0]
|
||||
vmulss %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vsubss %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x32,0x5c,0xd0]
|
||||
vsubss %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vdivss %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x32,0x5e,0xd0]
|
||||
vdivss %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vaddsd %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x33,0x58,0xd0]
|
||||
vaddsd %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vmulsd %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x33,0x59,0xd0]
|
||||
vmulsd %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vsubsd %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x33,0x5c,0xd0]
|
||||
vsubsd %xmm8, %xmm9, %xmm10
|
||||
|
||||
// CHECK: vdivsd %xmm8, %xmm9, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x33,0x5e,0xd0]
|
||||
vdivsd %xmm8, %xmm9, %xmm10
|
||||
|
||||
@ -212,7 +212,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
|
||||
|
||||
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
|
||||
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
|
||||
HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
|
||||
HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
|
||||
IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
|
||||
|
||||
@ -533,12 +532,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
|
||||
"Unexpected number of operands for MRMSrcRegFrm");
|
||||
HANDLE_OPERAND(roRegister)
|
||||
HANDLE_OPERAND(rmRegister)
|
||||
|
||||
if (HasVEX_4VPrefix)
|
||||
// FIXME: encoding of registers in AVX is in 1's complement form.
|
||||
HANDLE_OPTIONAL(rmRegister)
|
||||
else
|
||||
HANDLE_OPTIONAL(immediate)
|
||||
HANDLE_OPTIONAL(immediate)
|
||||
break;
|
||||
case X86Local::MRMSrcMem:
|
||||
// Operand 1 is a register operand in the Reg/Opcode field.
|
||||
|
||||
@ -52,8 +52,6 @@ private:
|
||||
bool HasOpSizePrefix;
|
||||
/// The hasREX_WPrefix field from the record
|
||||
bool HasREX_WPrefix;
|
||||
/// The hasVEX_4VPrefix field from the record
|
||||
bool HasVEX_4VPrefix;
|
||||
/// The hasLockPrefix field from the record
|
||||
bool HasLockPrefix;
|
||||
/// The isCodeGenOnly filed from the record
|
||||
|
||||
Loading…
Reference in New Issue
Block a user