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CodeGen: Use MachineInstr& in RegisterScavenging, NFC
Prefer MachineInstr& in order to avoid implicit conversions from MachineInstrBundleIterator to MachineInstr*. llvm-svn: 274888
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@ -97,14 +97,14 @@ void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) {
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void RegScavenger::determineKillsAndDefs() {
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assert(Tracking && "Must be tracking to determine kills and defs");
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MachineInstr *MI = MBBI;
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assert(!MI->isDebugValue() && "Debug values have no kills or defs");
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MachineInstr &MI = *MBBI;
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assert(!MI.isDebugValue() && "Debug values have no kills or defs");
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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KillRegUnits.reset();
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DefRegUnits.reset();
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for (const MachineOperand &MO : MI->operands()) {
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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TmpRegUnits.clear();
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for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
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@ -144,8 +144,8 @@ void RegScavenger::determineKillsAndDefs() {
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void RegScavenger::unprocess() {
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assert(Tracking && "Cannot unprocess because we're not tracking");
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MachineInstr *MI = MBBI;
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if (!MI->isDebugValue()) {
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MachineInstr &MI = *MBBI;
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if (!MI.isDebugValue()) {
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determineKillsAndDefs();
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// Commit the changes.
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@ -171,25 +171,25 @@ void RegScavenger::forward() {
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}
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MachineInstr *MI = MBBI;
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MachineInstr &MI = *MBBI;
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for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I) {
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if (I->Restore != MI)
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if (I->Restore != &MI)
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continue;
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I->Reg = 0;
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I->Restore = nullptr;
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}
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if (MI->isDebugValue())
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if (MI.isDebugValue())
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return;
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determineKillsAndDefs();
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// Verify uses and defs.
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#ifndef NDEBUG
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for (const MachineOperand &MO : MI->operands()) {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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@ -337,12 +337,11 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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return Survivor;
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}
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static unsigned getFrameIndexOperandNum(MachineInstr *MI) {
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static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
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unsigned i = 0;
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while (!MI->getOperand(i).isFI()) {
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI->getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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return i;
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}
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@ -435,7 +434,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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RC, TRI);
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MachineBasicBlock::iterator II = std::prev(I);
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unsigned FIOperandNum = getFrameIndexOperandNum(II);
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unsigned FIOperandNum = getFrameIndexOperandNum(*II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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// Restore the scavenged register before its use (or first terminator).
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@ -443,11 +442,11 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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RC, TRI);
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II = std::prev(UseMI);
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FIOperandNum = getFrameIndexOperandNum(II);
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FIOperandNum = getFrameIndexOperandNum(*II);
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TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
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}
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Scavenged[SI].Restore = std::prev(UseMI);
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Scavenged[SI].Restore = &*std::prev(UseMI);
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// Doing this here leads to infinite regress.
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// Scavenged[SI].Reg = SReg;
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