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[CodeGen] Use range-based for loops (NFC)

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This commit is contained in:
Kazu Hirata 2021-02-17 23:58:46 -08:00
parent e66d80ca10
commit 3414cd0493
8 changed files with 46 additions and 71 deletions
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7
lib/CodeGen/MachineSink.cpp
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@ -1097,11 +1097,8 @@ static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
// DBG_VALUE location as 'undef', indicating that any earlier variable
// location should be terminated as we've optimised away the value at this
// point.
for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
DBE = DbgValuesToSink.end();
DBI != DBE; ++DBI) {
MachineInstr *DbgMI = *DBI;
MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(*DBI);
for (MachineInstr *DbgMI : DbgValuesToSink) {
MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI);
SuccToSinkTo.insert(InsertPos, NewDbgMI);
if (!attemptDebugCopyProp(MI, *DbgMI))

8
lib/CodeGen/OptimizePHIs.cpp
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@ -83,8 +83,8 @@ bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) {
// introduce new opportunities, e.g., when i64 values are split up for
// 32-bit targets.
bool Changed = false;
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
Changed |= OptimizeBB(*I);
for (MachineBasicBlock &MBB : Fn)
Changed |= OptimizeBB(MBB);
return Changed;
}
@ -195,9 +195,7 @@ bool OptimizePHIs::OptimizeBB(MachineBasicBlock &MBB) {
// Check for dead PHI cycles.
PHIsInCycle.clear();
if (IsDeadPHICycle(MI, PHIsInCycle)) {
for (InstrSetIterator PI = PHIsInCycle.begin(), PE = PHIsInCycle.end();
PI != PE; ++PI) {
MachineInstr *PhiMI = *PI;
for (MachineInstr *PhiMI : PHIsInCycle) {
if (MII == PhiMI)
++MII;
PhiMI->eraseFromParent();

12
lib/CodeGen/ProcessImplicitDefs.cpp
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@ -143,18 +143,16 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
assert(WorkList.empty() && "Inconsistent worklist state");
for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
MFI != MFE; ++MFI) {
for (MachineBasicBlock &MBB : MF) {
// Scan the basic block for implicit defs.
for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
if (MBBI->isImplicitDef())
WorkList.insert(&*MBBI);
for (MachineInstr &MI : MBB)
if (MI.isImplicitDef())
WorkList.insert(&MI);
if (WorkList.empty())
continue;
LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
<< " implicit defs.\n");
Changed = true;

35
lib/CodeGen/PrologEpilogInserter.cpp
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@ -317,8 +317,8 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
return;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
for (MachineBasicBlock &BB : MF)
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I)
if (TII.isFrameInstr(*I)) {
unsigned Size = TII.getFrameSize(*I);
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
@ -337,10 +337,7 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
MFI.setAdjustsStack(AdjustsStack);
MFI.setMaxCallFrameSize(MaxCallFrameSize);
for (std::vector<MachineBasicBlock::iterator>::iterator
i = FrameSDOps.begin(), e = FrameSDOps.end(); i != e; ++i) {
MachineBasicBlock::iterator I = *i;
for (MachineBasicBlock::iterator I : FrameSDOps) {
// If call frames are not being included as part of the stack frame, and
// the target doesn't indicate otherwise, remove the call frame pseudos
// here. The sub/add sp instruction pairs are still inserted, but we don't
@ -772,9 +769,7 @@ static void AssignProtectedObjSet(const StackObjSet &UnassignedObjs,
int64_t &Offset, Align &MaxAlign,
unsigned Skew) {
for (StackObjSet::const_iterator I = UnassignedObjs.begin(),
E = UnassignedObjs.end(); I != E; ++I) {
int i = *I;
for (int i : UnassignedObjs) {
AdjustStackOffset(MFI, i, StackGrowsDown, Offset, MaxAlign, Skew);
ProtectedObjs.insert(i);
}
@ -888,9 +883,8 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
if (RS && EarlyScavengingSlots) {
SmallVector<int, 2> SFIs;
RS->getScavengingFrameIndices(SFIs);
for (SmallVectorImpl<int>::iterator I = SFIs.begin(),
IE = SFIs.end(); I != IE; ++I)
AdjustStackOffset(MFI, *I, StackGrowsDown, Offset, MaxAlign, Skew);
for (int SFI : SFIs)
AdjustStackOffset(MFI, SFI, StackGrowsDown, Offset, MaxAlign, Skew);
}
// FIXME: Once this is working, then enable flag will change to a target
@ -1050,9 +1044,8 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
if (RS && !EarlyScavengingSlots) {
SmallVector<int, 2> SFIs;
RS->getScavengingFrameIndices(SFIs);
for (SmallVectorImpl<int>::iterator I = SFIs.begin(),
IE = SFIs.end(); I != IE; ++I)
AdjustStackOffset(MFI, *I, StackGrowsDown, Offset, MaxAlign, Skew);
for (int SFI : SFIs)
AdjustStackOffset(MFI, SFI, StackGrowsDown, Offset, MaxAlign, Skew);
}
if (!TFI.targetHandlesStackFrameRounding()) {
@ -1089,12 +1082,12 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
LLVM_DEBUG(if (!SFIs.empty()) llvm::dbgs()
<< "Adjusting emergency spill slots!\n";);
int64_t Delta = Offset - OffsetBeforeAlignment;
for (SmallVectorImpl<int>::iterator I = SFIs.begin(), IE = SFIs.end();
I != IE; ++I) {
LLVM_DEBUG(llvm::dbgs() << "Adjusting offset of emergency spill slot #"
<< *I << " from " << MFI.getObjectOffset(*I););
MFI.setObjectOffset(*I, MFI.getObjectOffset(*I) - Delta);
LLVM_DEBUG(llvm::dbgs() << " to " << MFI.getObjectOffset(*I) << "\n";);
for (int SFI : SFIs) {
LLVM_DEBUG(llvm::dbgs()
<< "Adjusting offset of emergency spill slot #" << SFI
<< " from " << MFI.getObjectOffset(SFI););
MFI.setObjectOffset(SFI, MFI.getObjectOffset(SFI) - Delta);
LLVM_DEBUG(llvm::dbgs() << " to " << MFI.getObjectOffset(SFI) << "\n";);
}
}
}

8
lib/CodeGen/RDFGraph.cpp
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@ -994,8 +994,8 @@ RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
// For each stack in the map DefM, push the delimiter for block B on it.
void DataFlowGraph::markBlock(NodeId B, DefStackMap &DefM) {
// Push block delimiters.
for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I)
I->second.start_block(B);
for (auto &P : DefM)
P.second.start_block(B);
}
// Remove all definitions coming from block B from each stack in DefM.
@ -1003,8 +1003,8 @@ void DataFlowGraph::releaseBlock(NodeId B, DefStackMap &DefM) {
// Pop all defs from this block from the definition stack. Defs that were
// added to the map during the traversal of instructions will not have a
// delimiter, but for those, the whole stack will be emptied.
for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I)
I->second.clear_block(B);
for (auto &P : DefM)
P.second.clear_block(B);
// Finally, remove empty stacks from the map.
for (auto I = DefM.begin(), E = DefM.end(), NextI = I; I != E; I = NextI) {

10
lib/CodeGen/RegAllocBasic.cpp
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@ -286,16 +286,14 @@ MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg,
}
// Try to spill another interfering reg with less spill weight.
for (auto PhysRegI = PhysRegSpillCands.begin(),
PhysRegE = PhysRegSpillCands.end();
PhysRegI != PhysRegE; ++PhysRegI) {
if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
for (MCRegister &PhysReg : PhysRegSpillCands) {
if (!spillInterferences(VirtReg, PhysReg, SplitVRegs))
continue;
assert(!Matrix->checkInterference(VirtReg, *PhysRegI) &&
assert(!Matrix->checkInterference(VirtReg, PhysReg) &&
"Interference after spill.");
// Tell the caller to allocate to this newly freed physical register.
return *PhysRegI;
return PhysReg;
}
// No other spill candidates were found, so spill the current VirtReg.

5
lib/CodeGen/RegAllocFast.cpp
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@ -1253,9 +1253,8 @@ void RegAllocFast::allocateInstruction(MachineInstr &MI) {
// Displace clobbered registers.
const uint32_t *Mask = MO.getRegMask();
for (LiveRegMap::iterator LRI = LiveVirtRegs.begin(),
LRIE = LiveVirtRegs.end(); LRI != LRIE; ++LRI) {
MCPhysReg PhysReg = LRI->PhysReg;
for (const LiveReg &LR : LiveVirtRegs) {
MCPhysReg PhysReg = LR.PhysReg;
if (PhysReg != 0 && MachineOperand::clobbersPhysReg(Mask, PhysReg))
displacePhysReg(MI, PhysReg);
}

32
lib/CodeGen/RegAllocGreedy.cpp
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@ -1334,9 +1334,7 @@ bool RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
for (unsigned Bundle : NewBundles) {
// Look at all blocks connected to Bundle in the full graph.
ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
I != E; ++I) {
unsigned Block = *I;
for (unsigned Block : Blocks) {
if (!Todo.test(Block))
continue;
Todo.reset(Block);
@ -2653,18 +2651,16 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
// with VirtReg on PhysReg (or one of its aliases).
// Enqueue them for recoloring and perform the actual recoloring.
PQueue RecoloringQueue;
for (SmallLISet::iterator It = RecoloringCandidates.begin(),
EndIt = RecoloringCandidates.end();
It != EndIt; ++It) {
Register ItVirtReg = (*It)->reg();
enqueue(RecoloringQueue, *It);
for (LiveInterval *RC : RecoloringCandidates) {
Register ItVirtReg = RC->reg();
enqueue(RecoloringQueue, RC);
assert(VRM->hasPhys(ItVirtReg) &&
"Interferences are supposed to be with allocated variables");
// Record the current allocation.
VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
// unset the related struct.
Matrix->unassign(**It);
Matrix->unassign(*RC);
}
// Do as if VirtReg was assigned to PhysReg so that the underlying
@ -2698,22 +2694,18 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
// don't add it to NewVRegs because its physical register will be restored
// below. Other vregs in CurrentNewVRegs are created by calling
// selectOrSplit and should be added into NewVRegs.
for (SmallVectorImpl<Register>::iterator Next = CurrentNewVRegs.begin(),
End = CurrentNewVRegs.end();
Next != End; ++Next) {
if (RecoloringCandidates.count(&LIS->getInterval(*Next)))
for (Register &R : CurrentNewVRegs) {
if (RecoloringCandidates.count(&LIS->getInterval(R)))
continue;
NewVRegs.push_back(*Next);
NewVRegs.push_back(R);
}
for (SmallLISet::iterator It = RecoloringCandidates.begin(),
EndIt = RecoloringCandidates.end();
It != EndIt; ++It) {
Register ItVirtReg = (*It)->reg();
for (LiveInterval *RC : RecoloringCandidates) {
Register ItVirtReg = RC->reg();
if (VRM->hasPhys(ItVirtReg))
Matrix->unassign(**It);
Matrix->unassign(*RC);
MCRegister ItPhysReg = VirtRegToPhysReg[ItVirtReg];
Matrix->assign(**It, ItPhysReg);
Matrix->assign(*RC, ItPhysReg);
}
}