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[Hexagon] Crash in instruction selection for insert_vector_elt for HVX
A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
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@ -280,7 +280,7 @@ HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG)
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SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG);
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MVT SubVecTy = tyVector(ty(Ext), ElemTy);
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SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext),
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ValV, SubIdx, dl, SubVecTy, DAG);
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ValV, SubIdx, dl, ElemTy, DAG);
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// 3. Insert the 32-bit word back into the original vector.
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return InsertWord(VecV, Ins, ByteIdx);
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23
test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
Normal file
23
test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll
Normal file
@ -0,0 +1,23 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; REQUIRES: asserts
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; Check that this testcase compiles successfully.
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; CHECK: vextract
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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define void @fred() local_unnamed_addr #0 {
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b0:
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%v1 = load <64 x i8>, <64 x i8>* undef, align 64
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%v2 = insertelement <64 x i8> %v1, i8 0, i32 0
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br label %b3
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b3: ; preds = %b3, %b0
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%v4 = phi <64 x i8> [ %v2, %b0 ], [ %v6, %b3 ]
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%v5 = extractelement <64 x i8> %v4, i32 0
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%v6 = insertelement <64 x i8> %v4, i8 undef, i32 0
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br label %b3
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}
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attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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