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https://github.com/RPCS3/llvm-mirror.git
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[InstSimplify] Add some vector shift tests to show lack of DemandedElts support
This commit is contained in:
Simon Pilgrim
parent
5aeb5453b2
commit
3445f5ec2f
@ -377,6 +377,25 @@ define i1 @add(i32 %x, i32 %y) {
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ret i1 %c
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}
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define i1 @addv(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @addv(
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 0>
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; CHECK-NEXT: [[Q:%.*]] = lshr <2 x i32> [[Y:%.*]], <i32 1, i32 0>
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; CHECK-NEXT: [[R:%.*]] = or <2 x i32> [[Q]], <i32 1, i32 0>
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; CHECK-NEXT: [[S:%.*]] = add <2 x i32> [[L]], [[R]]
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; CHECK-NEXT: [[E:%.*]] = extractelement <2 x i32> [[S]], i32 0
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[E]], 0
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = lshr <2 x i32> %x, <i32 1, i32 0>
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%q = lshr <2 x i32> %y, <i32 1, i32 0>
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%r = or <2 x i32> %q, <i32 1, i32 0>
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%s = add <2 x i32> %l, %r
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%e = extractelement <2 x i32> %s, i32 0
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%c = icmp eq i32 %e, 0
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ret i1 %c
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}
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define i1 @add2(i8 %x, i8 %y) {
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; CHECK-LABEL: @add2(
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; CHECK-NEXT: ret i1 false
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@ -388,6 +407,23 @@ define i1 @add2(i8 %x, i8 %y) {
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ret i1 %c
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}
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define i1 @add2v(<2 x i8> %x, <2 x i8> %y) {
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; CHECK-LABEL: @add2v(
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; CHECK-NEXT: [[L:%.*]] = or <2 x i8> [[X:%.*]], <i8 0, i8 -128>
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; CHECK-NEXT: [[R:%.*]] = or <2 x i8> [[Y:%.*]], <i8 0, i8 -127>
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; CHECK-NEXT: [[S:%.*]] = add <2 x i8> [[L]], [[R]]
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; CHECK-NEXT: [[E:%.*]] = extractelement <2 x i8> [[S]], i32 1
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; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[E]], 0
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = or <2 x i8> %x, <i8 0, i8 128>
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%r = or <2 x i8> %y, <i8 0, i8 129>
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%s = add <2 x i8> %l, %r
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%e = extractelement <2 x i8> %s, i32 1
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%c = icmp eq i8 %e, 0
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ret i1 %c
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}
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define i1 @add3(i8 %x, i8 %y) {
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; CHECK-LABEL: @add3(
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; CHECK-NEXT: [[L:%.*]] = zext i8 [[X:%.*]] to i32
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@ -446,6 +482,23 @@ define i1 @addpowtwo(i32 %x, i32 %y) {
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ret i1 %c
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}
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define i1 @addpowtwov(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @addpowtwov(
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 1, i32 0>
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; CHECK-NEXT: [[R:%.*]] = shl <2 x i32> <i32 1, i32 0>, [[Y:%.*]]
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; CHECK-NEXT: [[S:%.*]] = add <2 x i32> [[L]], [[R]]
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; CHECK-NEXT: [[E:%.*]] = extractelement <2 x i32> [[S]], i32 0
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[E]], 0
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = lshr <2 x i32> %x, <i32 1, i32 0>
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%r = shl <2 x i32> <i32 1, i32 0>, %y
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%s = add <2 x i32> %l, %r
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%e = extractelement <2 x i32> %s, i32 0
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%c = icmp eq i32 %e, 0
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ret i1 %c
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}
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define i1 @or(i32 %x) {
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; CHECK-LABEL: @or(
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; CHECK-NEXT: ret i1 false
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@ -40,7 +40,7 @@ define i33 @ashr_amount_is_known_bogus(i33 %a, i33 %b) {
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define i16 @ashr_amount_is_zero(i16 %a, i16 %b) {
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; CHECK-LABEL: @ashr_amount_is_zero(
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; CHECK-NEXT: ret i16 %a
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; CHECK-NEXT: ret i16 [[A:%.*]]
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;
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%and = and i16 %b, 65520 ; 0xfff0
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%shr = ashr i16 %a, %and
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@ -49,7 +49,7 @@ define i16 @ashr_amount_is_zero(i16 %a, i16 %b) {
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define i300 @lshr_amount_is_zero(i300 %a, i300 %b) {
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; CHECK-LABEL: @lshr_amount_is_zero(
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; CHECK-NEXT: ret i300 %a
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; CHECK-NEXT: ret i300 [[A:%.*]]
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;
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%and = and i300 %b, 2048
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%shr = lshr i300 %a, %and
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@ -58,7 +58,7 @@ define i300 @lshr_amount_is_zero(i300 %a, i300 %b) {
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define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
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; CHECK-LABEL: @shl_amount_is_zero(
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; CHECK-NEXT: ret i9 %a
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; CHECK-NEXT: ret i9 [[A:%.*]]
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;
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%and = and i9 %b, 496 ; 0x1f0
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%shl = shl i9 %a, %and
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@ -70,8 +70,8 @@ define i9 @shl_amount_is_zero(i9 %a, i9 %b) {
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define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) {
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; CHECK-LABEL: @shl_amount_is_not_known_zero(
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; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8
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; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
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; CHECK-NEXT: [[AND:%.*]] = and i9 [[B:%.*]], -8
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; CHECK-NEXT: [[SHL:%.*]] = shl i9 [[A:%.*]], [[AND]]
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; CHECK-NEXT: ret i9 [[SHL]]
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;
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%and = and i9 %b, 504 ; 0x1f8
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@ -94,8 +94,8 @@ define <2 x i32> @ashr_vector_bogus(<2 x i32> %a, <2 x i32> %b) {
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; FIXME: This is undef, but computeKnownBits doesn't handle the union.
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define <2 x i32> @shl_vector_bogus(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_vector_bogus(
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> %b, <i32 32, i32 64>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]]
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[B:%.*]], <i32 32, i32 64>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[A:%.*]], [[OR]]
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; CHECK-NEXT: ret <2 x i32> [[SHL]]
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;
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%or = or <2 x i32> %b, <i32 32, i32 64>
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@ -105,7 +105,7 @@ define <2 x i32> @shl_vector_bogus(<2 x i32> %a, <2 x i32> %b) {
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define <2 x i32> @lshr_vector_zero(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @lshr_vector_zero(
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; CHECK-NEXT: ret <2 x i32> %a
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; CHECK-NEXT: ret <2 x i32> [[A:%.*]]
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;
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%and = and <2 x i32> %b, <i32 64, i32 256>
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%shr = lshr <2 x i32> %a, %and
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@ -115,7 +115,7 @@ define <2 x i32> @lshr_vector_zero(<2 x i32> %a, <2 x i32> %b) {
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; Make sure that weird vector types work too.
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define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) {
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; CHECK-LABEL: @shl_vector_zero(
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; CHECK-NEXT: ret <2 x i15> %a
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; CHECK-NEXT: ret <2 x i15> [[A:%.*]]
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;
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%and = and <2 x i15> %b, <i15 1024, i15 1024>
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%shl = shl <2 x i15> %a, %and
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@ -124,8 +124,8 @@ define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) {
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define <2 x i32> @shl_vector_for_real(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: @shl_vector_for_real(
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %b, <i32 3, i32 3>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]]
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[B:%.*]], <i32 3, i32 3>
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[A:%.*]], [[AND]]
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; CHECK-NEXT: ret <2 x i32> [[SHL]]
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;
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%and = and <2 x i32> %b, <i32 3, i32 3> ; a necessary mask op
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@ -139,7 +139,7 @@ define <2 x i32> @shl_vector_for_real(<2 x i32> %a, <2 x i32> %b) {
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define i1 @shl_i1(i1 %a, i1 %b) {
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; CHECK-LABEL: @shl_i1(
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; CHECK-NEXT: ret i1 %a
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; CHECK-NEXT: ret i1 [[A:%.*]]
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;
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%shl = shl i1 %a, %b
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ret i1 %shl
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@ -179,6 +179,19 @@ define <2 x i8> @lshr_ctlz_zero_is_undef_splat_vec(<2 x i8> %x) {
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ret <2 x i8> %sh
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}
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define i8 @lshr_ctlz_zero_is_undef_vec(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_ctlz_zero_is_undef_vec(
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; CHECK-NEXT: [[CT:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[X:%.*]], i1 true)
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; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[CT]], <i8 3, i8 0>
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; CHECK-NEXT: [[EX:%.*]] = extractelement <2 x i8> [[SH]], i32 0
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; CHECK-NEXT: ret i8 [[EX]]
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;
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%ct = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %x, i1 true)
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%sh = lshr <2 x i8> %ct, <i8 3, i8 0>
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%ex = extractelement <2 x i8> %sh, i32 0
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ret i8 %ex
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}
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define <2 x i8> @lshr_cttz_zero_is_undef_splat_vec(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_cttz_zero_is_undef_splat_vec(
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; CHECK-NEXT: ret <2 x i8> zeroinitializer
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@ -188,3 +201,16 @@ define <2 x i8> @lshr_cttz_zero_is_undef_splat_vec(<2 x i8> %x) {
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ret <2 x i8> %sh
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}
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define i8 @lshr_cttz_zero_is_undef_vec(<2 x i8> %x) {
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; CHECK-LABEL: @lshr_cttz_zero_is_undef_vec(
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; CHECK-NEXT: [[CT:%.*]] = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> [[X:%.*]], i1 true)
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; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[CT]], <i8 3, i8 0>
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; CHECK-NEXT: [[EX:%.*]] = extractelement <2 x i8> [[SH]], i32 0
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; CHECK-NEXT: ret i8 [[EX]]
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;
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%ct = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 true)
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%sh = lshr <2 x i8> %ct, <i8 3, i8 0>
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%ex = extractelement <2 x i8> %sh, i32 0
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ret i8 %ex
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}
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