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SelectionDAG: Lower some range metadata to AssertZext
If a range has a lower bound of 0, add an AssertZext from the nearest floor power of two. This allows operations with some workitem intrinsics with known maximum ranges to use fast 24-bit multiplies. llvm-svn: 260109
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@ -3721,7 +3721,8 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
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if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
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if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
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EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
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EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
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Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
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Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
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}
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} else
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Result = lowerRangeToAssertZExt(DAG, I, Result);
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setValue(&I, Result);
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setValue(&I, Result);
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}
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}
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@ -5419,8 +5420,11 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
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.setTailCall(isTailCall);
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.setTailCall(isTailCall);
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std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
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std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
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if (Result.first.getNode())
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if (Result.first.getNode()) {
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setValue(CS.getInstruction(), Result.first);
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const Instruction *Inst = CS.getInstruction();
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Result.first = lowerRangeToAssertZExt(DAG, *Inst, Result.first);
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setValue(Inst, Result.first);
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}
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}
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}
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/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
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/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
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@ -6716,6 +6720,39 @@ void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
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DAG.getSrcValue(I.getArgOperand(1))));
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DAG.getSrcValue(I.getArgOperand(1))));
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}
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}
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SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
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const Instruction &I,
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SDValue Op) {
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const MDNode *Range = I.getMetadata(LLVMContext::MD_range);
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if (!Range)
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return Op;
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Constant *Lo = cast<ConstantAsMetadata>(Range->getOperand(0))->getValue();
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if (!Lo->isNullValue())
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return Op;
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Constant *Hi = cast<ConstantAsMetadata>(Range->getOperand(1))->getValue();
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unsigned Bits = cast<ConstantInt>(Hi)->getValue().logBase2();
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EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);
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SDLoc SL = getCurSDLoc();
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SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(),
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Op, DAG.getValueType(SmallVT));
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unsigned NumVals = Op.getNode()->getNumValues();
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if (NumVals == 1)
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return ZExt;
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(ZExt);
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for (unsigned I = 1; I != NumVals; ++I)
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Ops.push_back(Op.getValue(I));
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return DAG.getMergeValues(Ops, SL);
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}
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/// \brief Lower an argument list according to the target calling convention.
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/// \brief Lower an argument list according to the target calling convention.
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///
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///
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/// \return A tuple of <return-value, token-chain>
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/// \return A tuple of <return-value, token-chain>
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@ -708,6 +708,11 @@ public:
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void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
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void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
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const BasicBlock *EHPadBB = nullptr);
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const BasicBlock *EHPadBB = nullptr);
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// Lower range metadata from 0 to N to assert zext to an integer of nearest
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// floor power of two.
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SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I,
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SDValue Op);
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std::pair<SDValue, SDValue> lowerCallOperands(
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std::pair<SDValue, SDValue> lowerCallOperands(
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ImmutableCallSite CS,
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ImmutableCallSite CS,
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unsigned ArgIdx,
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unsigned ArgIdx,
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44
test/CodeGen/AArch64/lower-range-metadata-func-call.ll
Normal file
44
test/CodeGen/AArch64/lower-range-metadata-func-call.ll
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@ -0,0 +1,44 @@
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; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
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; and can be eliminated
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; CHECK-LABEL: {{^}}test_call_known_max_range:
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; CHECK: bl foo
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; CHECK-NOT: and
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; CHECK: ret
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define i32 @test_call_known_max_range() #0 {
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entry:
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%id = tail call i32 @foo(), !range !0
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%and = and i32 %id, 1023
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ret i32 %and
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}
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; CHECK-LABEL: {{^}}test_call_known_trunc_1_bit_range:
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; CHECK: bl foo
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; CHECK: and w{{[0-9]+}}, w0, #0x1ff
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; CHECK: ret
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define i32 @test_call_known_trunc_1_bit_range() #0 {
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entry:
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%id = tail call i32 @foo(), !range !0
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%and = and i32 %id, 511
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ret i32 %and
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}
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; CHECK-LABEL: {{^}}test_call_known_max_range_m1:
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; CHECK: bl foo
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; CHECK: and w{{[0-9]+}}, w0, #0xff
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; CHECK: ret
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define i32 @test_call_known_max_range_m1() #0 {
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entry:
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%id = tail call i32 @foo(), !range !1
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%and = and i32 %id, 255
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ret i32 %and
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}
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declare i32 @foo()
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attributes #0 = { norecurse nounwind }
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attributes #1 = { nounwind readnone }
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!0 = !{i32 0, i32 1024}
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!1 = !{i32 0, i32 1023}
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46
test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
Normal file
46
test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll
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@ -0,0 +1,46 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
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; and can be eliminated
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
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; CHECK-NOT: v0
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; CHECK: {{flat|buffer}}_store_dword v0
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define void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%and = and i32 %id, 1023
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range:
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; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0
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; CHECK: {{flat|buffer}}_store_dword [[MASKED]]
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define void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%and = and i32 %id, 511
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1:
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; CHECK-NOT: v0
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; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0
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; CHECK: {{flat|buffer}}_store_dword [[MASKED]]
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define void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1
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%and = and i32 %id, 255
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { norecurse nounwind }
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attributes #1 = { nounwind readnone }
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!0 = !{i32 0, i32 1024}
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!1 = !{i32 0, i32 1023}
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