RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[DAGCombiner] Do not generate ISD::ADDE node if adde is not legal for the target when combine ISD::TRUNC node

Browse Source 
Do not combine (trunc adde(X, Y, Carry)) into (adde trunc(X), trunc(Y), Carry), 
if adde is not legal for the target. Even it's at type-legalize phase. 
Because adde is special and will not be legalized at operation-legalize phase later.

This fixes: PR40922
https://bugs.llvm.org/show_bug.cgi?id=40922

Differential Revision: https://reviews.llvm.org//D60854

llvm-svn: 359532
This commit is contained in:
Zi Xuan Wu 2019-04-30 03:01:14 +00:00
parent ef866621d0
commit 34efb823fc
3 changed files with 41 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -10257,7 +10257,9 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
// When the adde's carry is not used.
if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
N0.hasOneUse() && !N0.getNode()->hasAnyUseOfValue(1) &&
(!LegalOperations || TLI.isOperationLegal(N0.getOpcode(), VT))) {
// We only do for addcarry before legalize operation
((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) ||
TLI.isOperationLegal(N0.getOpcode(), VT))) {
SDLoc SL(N);
auto X = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(0));
auto Y = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));

5
test/CodeGen/PowerPC/pr39815.ll
View File

@ -20,10 +20,9 @@ entry:
; CHECK: # %bb.0:
; CHECK-DAG: addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK-DAG: ld [[REG3:[0-9]+]], [[VAR1]]@toc@l([[REG1]])
; CHECK-DAG: lbz [[REG4:[0-9]+]], 0([[REG3]])
; CHECK-DAG: lwz [[REG4:[0-9]+]], 0([[REG3]])
; CHECK-DAG: addic [[REG5:[0-9]+]], [[REG3]], -1
; CHECK-DAG: extsb [[REG6:[0-9]+]], [[REG4]]
; CHECK-DAG: addze [[REG7:[0-9]+]], [[REG6]]
; CHECK-DAG: addze [[REG7:[0-9]+]], [[REG4]]
; CHECK-DAG: addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
; CHECK-DAG: andi. [[REG9:[0-9]+]], [[REG7]], 5
; CHECK-DAG: stb [[REG9]], [[VAR2]]@toc@l([[REG8]])

36
test/CodeGen/PowerPC/pr40922.ll Normal file
View File

@ -0,0 +1,36 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
; Test case adapted from PR40922.
@a.b = internal global i32 0, align 4
define i32 @a() {
entry:
%call = tail call i32 bitcast (i32 (...)* @d to i32 ()*)()
%0 = load i32, i32* @a.b, align 4
%conv = zext i32 %0 to i64
%add = add nuw nsw i64 %conv, 6
%and = and i64 %add, 8589934575
%cmp = icmp ult i64 %and, %conv
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%call3 = tail call i32 bitcast (i32 (...)* @e to i32 ()*)()
br label %if.end
if.end: ; preds = %if.then, %entry
store i32 %call, i32* @a.b, align 4
ret i32 undef
}
; CHECK-LABEL: @a
; CHECK: li 5, 0
; CHECK: mr 30, 3
; CHECK: addic 6, 4, 6
; CHECK: addze 5, 5
; CHECK: rlwinm 6, 6, 0, 28, 26
; CHECK: andi. 5, 5, 1
declare i32 @d(...)
declare i32 @e(...)