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[AMDGPU] Update code object description
- Use ELF header flags to identify processor. - Remove isa note record. - Add target feature section. - Make metadata for NumVGPRs, NumSGPRs and MaxFlatWorkGroupSize required. - Add FixedWorkGroupSize to CodeProps metadata. - Add ReqdWorkGroupSize* to kernel descriptor and move MaxFlatWorkGroupSize to be adjacent. - Move IsXNACKEnabled in the kernel descriptor to be at the end of the unused flags. - Remove IsDynamicCallStack from the metadata and kernel descriptor. - Remove legacy debugger metadata. - Remove old XNACK enabled processor names. Differential Revision: https://reviews.llvm.org/D39828 llvm-svn: 317855
This commit is contained in:
Tony Tye
parent
befcc521fc
commit
34f9af3e72
@ -23,50 +23,55 @@ Target Triples
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Use the ``clang -target <Architecture>-<Vendor>-<OS>-<Environment>`` option to
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specify the target triple:
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.. table:: AMDGPU Target Triples
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:name: amdgpu-target-triples-table
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.. table:: AMDGPU Architectures
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:name: amdgpu-architecture-table
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============ ======== ========= ===========
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Architecture Vendor OS Environment
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============ ======== ========= ===========
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r600 amd <empty> <empty>
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amdgcn amd <empty> <empty>
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amdgcn amd amdhsa <empty>
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amdgcn amd amdhsa opencl
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amdgcn amd amdhsa amdgizcl
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amdgcn amd amdhsa amdgiz
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amdgcn amd amdhsa hcc
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============ ======== ========= ===========
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============ ==============================================================
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Architecture Description
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============ ==============================================================
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``r600`` AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.
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``amdgcn`` AMD GPUs GCN GFX6 onwards for graphics and compute shaders.
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============ ==============================================================
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``r600-amd--``
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Supports AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders executed on
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the MESA runtime.
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.. table:: AMDGPU Vendors
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:name: amdgpu-vendor-table
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``amdgcn-amd--``
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Supports AMD GPUs GCN GFX6 onwards for graphics and compute shaders executed on
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the MESA runtime.
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============ ==============================================================
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Vendor Description
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============ ==============================================================
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``amd`` Can be used for all AMD GPU usage.
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``mesa3d`` Can be used if the OS is ``mesa3d``.
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============ ==============================================================
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``amdgcn-amd-amdhsa-``
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Supports AMD GCN GPUs GFX6 onwards for compute kernels executed on HSA [HSA]_
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compatible runtimes such as AMD's ROCm [AMD-ROCm]_.
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.. table:: AMDGPU Operating Systems
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:name: amdgpu-os-table
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``amdgcn-amd-amdhsa-opencl``
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Supports AMD GCN GPUs GFX6 onwards for OpenCL compute kernels executed on HSA
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[HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. See
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:ref:`amdgpu-opencl`.
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============== ============================================================
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OS Description
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============== ============================================================
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*<empty>* Defaults to the *unknown* OS.
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``amdhsa`` Compute kernels executed on HSA [HSA]_ compatible runtimes
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such as AMD's ROCm [AMD-ROCm]_.
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``amdpal`` Graphic shaders and compute kernels executed on AMD PAL
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runtime.
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``mesa3d`` Graphic shaders and compute kernels executed on Mesa 3D
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runtime.
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============== ============================================================
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``amdgcn-amd-amdhsa-amdgizcl``
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Same as ``amdgcn-amd-amdhsa-opencl`` except a different address space mapping
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is used (see :ref:`amdgpu-address-spaces`).
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.. table:: AMDGPU Environments
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:name: amdgpu-environment-table
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``amdgcn-amd-amdhsa-amdgiz``
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Same as ``amdgcn-amd-amdhsa-`` except a different address space mapping is
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============ ==============================================================
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Environment Description
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============ ==============================================================
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*<empty>* Defaults to ``opencl``.
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``opencl`` OpenCL compute kernel (see :ref:`amdgpu-opencl`).
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``amdgizcl`` Same as ``opencl`` except a different address space mapping is
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used (see :ref:`amdgpu-address-spaces`).
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``amdgcn-amd-amdhsa-hcc``
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Supports AMD GCN GPUs GFX6 onwards for AMD HC language compute kernels
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executed on HSA [HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. See
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:ref:`amdgpu-hcc`.
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``amdgiz`` Same as ``opencl`` except a different address space mapping is
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used (see :ref:`amdgpu-address-spaces`).
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``hcc`` AMD HC language compute kernel (see :ref:`amdgpu-hcc`).
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============ ==============================================================
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.. _amdgpu-processors:
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@ -77,51 +82,51 @@ Use the ``clang -mcpu <Processor>`` option to specify the AMD GPU processor. The
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names from both the *Processor* and *Alternative Processor* can be used.
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.. table:: AMDGPU Processors
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:name: amdgpu-processors-table
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:name: amdgpu-processor-table
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========== =========== ============ ===== ======= ==================
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Processor Alternative Target dGPU/ Runtime Example
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=========== =============== ============ ===== ======= ==================
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Processor Alternative Target dGPU/ ROCm Example
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Processor Triple APU Support Products
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Architecture
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========== =========== ============ ===== ======= ==================
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=========== =============== ============ ===== ======= ==================
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**Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_
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--------------------------------------------------------------------
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r600 r600 dGPU
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r630 r600 dGPU
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rs880 r600 dGPU
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rv670 r600 dGPU
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-------------------------------------------------------------------------
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``r600`` ``r600`` dGPU
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``r630`` ``r600`` dGPU
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``rs880`` ``r600`` dGPU
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``rv670`` ``r600`` dGPU
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**Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_
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--------------------------------------------------------------------
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rv710 r600 dGPU
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rv730 r600 dGPU
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rv770 r600 dGPU
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-------------------------------------------------------------------------
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``rv710`` ``r600`` dGPU
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``rv730`` ``r600`` dGPU
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``rv770`` ``r600`` dGPU
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**Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_
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--------------------------------------------------------------------
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cedar r600 dGPU
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redwood r600 dGPU
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sumo r600 dGPU
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juniper r600 dGPU
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cypress r600 dGPU
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-------------------------------------------------------------------------
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``cedar`` ``r600`` dGPU
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``redwood`` ``r600`` dGPU
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``sumo`` ``r600`` dGPU
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``juniper`` ``r600`` dGPU
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``cypress`` ``r600`` dGPU
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**Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_
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--------------------------------------------------------------------
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barts r600 dGPU
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turks r600 dGPU
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caicos r600 dGPU
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cayman r600 dGPU
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-------------------------------------------------------------------------
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``barts`` ``r600`` dGPU
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``turks`` ``r600`` dGPU
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``caicos`` ``r600`` dGPU
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``cayman`` ``r600`` dGPU
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**GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_
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--------------------------------------------------------------------
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gfx600 - tahiti amdgcn dGPU
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gfx601 - pitcairn amdgcn dGPU
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- verde
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- oland
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- hainan
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-------------------------------------------------------------------------
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``gfx600`` - ``tahiti`` ``amdgcn`` dGPU
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``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU
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- ``verde``
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- ``oland``
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- ``hainan``
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**GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_
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--------------------------------------------------------------------
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gfx700 - bonaire amdgcn dGPU - Radeon HD 7790
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-------------------------------------------------------------------------
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``gfx700`` - ``bonaire`` ``amdgcn`` dGPU - Radeon HD 7790
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- Radeon HD 8770
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- R7 260
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- R7 260X
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\ - kaveri amdgcn APU - A6-7000
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\ - ``kaveri`` ``amdgcn`` APU - A6-7000
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- A6 Pro-7050B
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- A8-7100
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- A8 Pro-7150B
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@ -131,16 +136,16 @@ names from both the *Processor* and *Alternative Processor* can be used.
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- A8-7200P
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- A10-7400P
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- FX-7600P
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gfx701 - hawaii amdgcn dGPU ROCm - FirePro W8100
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``gfx701`` - ``hawaii`` ``amdgcn`` dGPU ROCm - FirePro W8100
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- FirePro W9100
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- FirePro S9150
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- FirePro S9170
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gfx702 dGPU ROCm - Radeon R9 290
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``gfx702`` ``amdgcn`` dGPU ROCm - Radeon R9 290
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- Radeon R9 290x
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- Radeon R390
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- Radeon R390x
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gfx703 - kabini amdgcn APU - E1-2100
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- mullins - E1-2200
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``gfx703`` - ``kabini`` ``amdgcn`` APU - E1-2100
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- ``mullins`` - E1-2200
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- E1-2500
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- E2-3000
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- E2-3800
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@ -149,8 +154,8 @@ names from both the *Processor* and *Alternative Processor* can be used.
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- A6-5200
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- A4 Pro-3340B
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**GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_
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--------------------------------------------------------------------
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gfx800 - iceland amdgcn dGPU - FirePro S7150
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-------------------------------------------------------------------------
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``gfx800`` - ``iceland`` ``amdgcn`` dGPU - FirePro S7150
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- FirePro S7100
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- FirePro W7100
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- Radeon R285
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@ -158,58 +163,98 @@ names from both the *Processor* and *Alternative Processor* can be used.
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- Radeon R9 385
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- Mobile FirePro
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M7170
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gfx801 - carrizo amdgcn APU - A6-8500P
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``gfx801`` - ``carrizo`` ``amdgcn`` APU - A6-8500P
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- Pro A6-8500B
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- A8-8600P
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- Pro A8-8600B
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- FX-8800P
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- Pro A12-8800B
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\ amdgcn APU ROCm - A10-8700P
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\ ``amdgcn`` APU ROCm - A10-8700P
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- Pro A10-8700B
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- A10-8780P
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\ amdgcn APU - A10-9600P
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\ ``amdgcn`` APU - A10-9600P
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- A10-9630P
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- A12-9700P
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- A12-9730P
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- FX-9800P
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- FX-9830P
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\ amdgcn APU - E2-9010
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\ ``amdgcn`` APU - E2-9010
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- A6-9210
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- A9-9410
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gfx802 - tonga amdgcn dGPU ROCm Same as gfx800
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gfx803 - fiji amdgcn dGPU ROCm - Radeon R9 Nano
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``gfx802`` - ``tonga`` ``amdgcn`` dGPU ROCm Same as gfx800
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``gfx803`` - ``fiji`` ``amdgcn`` dGPU ROCm - Radeon R9 Nano
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- Radeon R9 Fury
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- Radeon R9 FuryX
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- Radeon Pro Duo
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- FirePro S9300x2
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- Radeon Instinct MI8
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\ - polaris10 amdgcn dGPU ROCm - Radeon RX 470
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\ - ``polaris10`` ``amdgcn`` dGPU ROCm - Radeon RX 470
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- Radeon RX 480
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- Radeon Instinct MI6
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\ - polaris11 amdgcn dGPU ROCm - Radeon RX 460
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gfx804 amdgcn dGPU Same as gfx803
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gfx810 - stoney amdgcn APU
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\ - ``polaris11`` ``amdgcn`` dGPU ROCm - Radeon RX 460
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``gfx810`` - ``stoney`` ``amdgcn`` APU
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**GCN GFX9** [AMD-GCN-GFX9]_
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--------------------------------------------------------------------
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gfx900 amdgcn dGPU - Radeon Vega
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-------------------------------------------------------------------------
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``gfx900`` ``amdgcn`` dGPU ROCm - Radeon Vega
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Frontier Edition
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- Radeon RX Vega 56
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- Radeon RX Vega 64
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- Radeon RX Vega 64
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Liquid
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- Radeon Instinct MI25
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gfx901 amdgcn dGPU ROCm Same as gfx900
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except XNACK is
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enabled
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gfx902 amdgcn APU *TBA*
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``gfx902`` ``amdgcn`` APU *TBA*
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.. TODO
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Add product
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names.
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gfx903 amdgcn APU Same as gfx902
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except XNACK is
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enabled
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========== =========== ============ ===== ======= ==================
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=========== =============== ============ ===== ======= ==================
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.. _amdgpu-target-features:
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Target Features
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---------------
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Target features control how code is generated to support certain
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features. Not all target features are supported by all processors. The
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runtime must ensure that the features supported by the device used to
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execute the code match the features enabled when generating the
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code. A mismatch of features may result in incorrect execution, or a
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reduction in performance.
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Use the ``clang -m[no-]<TargetFeature>`` option to specify the AMD GPU
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target features.
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For example:
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``-mxnack``
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Enable the *XNACK* feature.
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``-mno-xnack``
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Disable the *XNACK* feature.
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.. table:: AMDGPU Target Features
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:name: amdgpu-target-feature-table
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============== ======== ==================================================
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Target Feature Default Description
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============== ======== ==================================================
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-m[no-]xnack disabled Enable/disable generating code that has
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memory clauses that are compatible with
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having XNACK replay enabled.
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This is used for demand paging and page
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migration. If XNACK replay is enabled in
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the device, then if a page fault occurs
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the code may execute incorrectly if the
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XNACK feature is not enabled. Executing
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code that has the feature enabled on a
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device that does not have XNACK replay
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enabled will execute correctly, but may
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be less performant than code with the
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feature disabled.
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This feature is supported by the
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``amdgcn`` architecture for GFX7-GFX9.
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============== ======== ==================================================
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.. _amdgpu-address-spaces:
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@ -268,14 +313,14 @@ The memory model supported is based on the HSA memory model [HSA]_ which is
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based in turn on HRF-indirect with scope inclusion [HRF]_. The happens-before
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relation is transitive over the synchonizes-with relation independent of scope,
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and synchonizes-with allows the memory scope instances to be inclusive (see
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table :ref:`amdgpu-amdhsa-llvm-sync-scopes-amdhsa-table`).
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table :ref:`amdgpu-amdhsa-llvm-sync-scopes-table`).
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This is different to the OpenCL [OpenCL]_ memory model which does not have scope
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inclusion and requires the memory scopes to exactly match. However, this
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is conservatively correct for OpenCL.
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.. table:: AMDHSA LLVM Sync Scopes for AMDHSA
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:name: amdgpu-amdhsa-llvm-sync-scopes-amdhsa-table
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.. table:: AMDHSA LLVM Sync Scopes
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:name: amdgpu-amdhsa-llvm-sync-scopes-table
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================ ==========================================================
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LLVM Sync Scope Description
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@ -364,16 +409,18 @@ The AMDGPU backend uses the following ELF header:
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========================== ===============================
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``e_ident[EI_CLASS]`` ``ELFCLASS64``
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``e_ident[EI_DATA]`` ``ELFDATA2LSB``
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``e_ident[EI_OSABI]`` ``ELFOSABI_AMDGPU_HSA``,
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``ELFOSABI_AMDGPU_PAL`` or
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``ELFOSABI_AMDGPU_MESA3D``
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``e_ident[EI_ABIVERSION]`` ``ELFABIVERSION_AMDGPU_HSA``,
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``ELFABIVERSION_AMDGPU_PAL`` or
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``ELFABIVERSION_AMDGPU_MESA3D``
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``e_type`` ``ET_REL`` or ``ET_DYN``
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``e_ident[EI_OSABI]`` - ``ELFOSABI_NONE``
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- ``ELFOSABI_AMDGPU_HSA``
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- ``ELFOSABI_AMDGPU_PAL``
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- ``ELFOSABI_AMDGPU_MESA3D``
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``e_ident[EI_ABIVERSION]`` - ``ELFABIVERSION_AMDGPU_HSA``
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- ``ELFABIVERSION_AMDGPU_PAL``
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- ``ELFABIVERSION_AMDGPU_MESA3D``
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``e_type`` - ``ET_REL``
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- ``ET_DYN``
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``e_machine`` ``EM_AMDGPU``
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``e_entry`` 0
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``e_flags`` 0
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``e_flags`` See :ref:`amdgpu-elf-header-e_flags-table`
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========================== ===============================
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..
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@ -385,6 +432,7 @@ The AMDGPU backend uses the following ELF header:
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Name Value
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=============================== =====
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``EM_AMDGPU`` 224
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``ELFOSABI_NONE`` 0
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``ELFOSABI_AMDGPU_HSA`` 64
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``ELFOSABI_AMDGPU_PAL`` 65
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``ELFOSABI_AMDGPU_MESA3D`` 66
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@ -394,23 +442,27 @@ The AMDGPU backend uses the following ELF header:
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=============================== =====
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``e_ident[EI_CLASS]``
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The ELF class is always ``ELFCLASS64``. The AMDGPU backend only supports 64
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The ELF class is:
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* ``ELFCLASS32`` for ``r600`` architecture.
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* ``ELFCLASS64`` for ``amdgcn`` architecture which only supports 64
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bit applications.
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``e_ident[EI_DATA]``
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All AMDGPU targets use ELFDATA2LSB for little-endian byte ordering.
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All AMDGPU targets use ``ELFDATA2LSB`` for little-endian byte ordering.
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``e_ident[EI_OSABI]``
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One of the following AMD GPU architecture specific OS ABIs:
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One of the following AMD GPU architecture specific OS ABIs
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(see :ref:`amdgpu-os-table`):
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* ``ELFOSABI_AMDGPU_HSA`` is used to specify that the code object conforms to
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the AMD HSA runtime ABI [HSA]_.
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* ``ELFOSABI_NONE`` for *unknown* OS.
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* ``ELFOSABI_AMDGPU_PAL`` is used to specify that the code object conforms to
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the AMD PAL runtime ABI.
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* ``ELFOSABI_AMDGPU_HSA`` for ``amdhsa`` OS.
|
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* ``ELFOSABI_AMDGPU_MESA3D`` is used to specify that the code object conforms
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to the AMD MESA runtime ABI.
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* ``ELFOSABI_AMDGPU_PAL`` for ``amdpal`` OS.
|
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* ``ELFOSABI_AMDGPU_MESA3D`` for ``mesa3D`` OS.
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``e_ident[EI_ABIVERSION]``
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The ABI version of the AMD GPU architecture specific OS ABI to which the code
|
||||
@ -423,7 +475,7 @@ The AMDGPU backend uses the following ELF header:
|
||||
runtime ABI.
|
||||
|
||||
* ``ELFABIVERSION_AMDGPU_MESA3D`` is used to specify the version of AMD MESA
|
||||
runtime ABI.
|
||||
3D runtime ABI.
|
||||
|
||||
``e_type``
|
||||
Can be one of the following values:
|
||||
@ -439,17 +491,74 @@ The AMDGPU backend uses the following ELF header:
|
||||
The AMD HSA runtime loader requires a ``ET_DYN`` code object.
|
||||
|
||||
``e_machine``
|
||||
The value ``EM_AMDGPU`` is used for the machine for all members of the AMD GPU
|
||||
architecture family. The specific member is specified in the
|
||||
``NT_AMD_AMDGPU_ISA`` entry in the ``.note`` section (see
|
||||
:ref:`amdgpu-note-records`).
|
||||
The value ``EM_AMDGPU`` is used for the machine for all processors supported
|
||||
by the ``r600`` and ``amdgcn`` architectures (see
|
||||
:ref:`amdgpu-processor-table`). The specific processor is specified in the
|
||||
``EF_AMDGPU_MACH`` bit field of the ``e_flags`` (see
|
||||
:ref:`amdgpu-elf-header-e_flags-table`).
|
||||
|
||||
``e_entry``
|
||||
The entry point is 0 as the entry points for individual kernels must be
|
||||
selected in order to invoke them through AQL packets.
|
||||
|
||||
``e_flags``
|
||||
The value is 0 as no flags are used.
|
||||
The AMDGPU backend uses the following ELF header flags:
|
||||
|
||||
.. table:: AMDGPU ELF Header ``e_flags``
|
||||
:name: amdgpu-elf-header-e_flags-table
|
||||
|
||||
================================= ========== =============================
|
||||
Name Value Description
|
||||
================================= ========== =============================
|
||||
**AMDGPU Processor Flag** See :ref:`amdgpu-processor-table`.
|
||||
-------------------------------------------- -----------------------------
|
||||
``EF_AMDGPU_MACH`` 0x000000ff AMDGPU processor selection
|
||||
mask for
|
||||
``EF_AMDGPU_MACH_xxx`` values
|
||||
defined in
|
||||
:ref:`amdgpu-ef-amdgpu-mach-table`.
|
||||
================================= ========== =============================
|
||||
|
||||
.. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
|
||||
:name: amdgpu-ef-amdgpu-mach-table
|
||||
|
||||
================================= ========== =============================
|
||||
Name Value Description (see
|
||||
:ref:`amdgpu-processor-table`)
|
||||
================================= ========== =============================
|
||||
``EF_AMDGPU_MACH_NONE`` 0 *not specified*
|
||||
``EF_AMDGPU_MACH_R600_R600`` 1 ``r600``
|
||||
``EF_AMDGPU_MACH_R600_R630`` 2 ``r630``
|
||||
``EF_AMDGPU_MACH_R600_RS880`` 3 ``rs880``
|
||||
``EF_AMDGPU_MACH_R600_RV670`` 4 ``rv670``
|
||||
``EF_AMDGPU_MACH_R600_RV710`` 5 ``rv710``
|
||||
``EF_AMDGPU_MACH_R600_RV730`` 6 ``rv730``
|
||||
``EF_AMDGPU_MACH_R600_RV770`` 7 ``rv770``
|
||||
``EF_AMDGPU_MACH_R600_CEDAR`` 8 ``cedar``
|
||||
``EF_AMDGPU_MACH_R600_REDWOOD`` 9 ``redwood``
|
||||
``EF_AMDGPU_MACH_R600_SUMO`` 10 ``sumo``
|
||||
``EF_AMDGPU_MACH_R600_JUNIPER`` 11 ``juniper``
|
||||
``EF_AMDGPU_MACH_R600_CYPRESS`` 12 ``cypress``
|
||||
``EF_AMDGPU_MACH_R600_BARTS`` 13 ``barts``
|
||||
``EF_AMDGPU_MACH_R600_TURKS`` 14 ``turks``
|
||||
``EF_AMDGPU_MACH_R600_CAICOS`` 15 ``caicos``
|
||||
``EF_AMDGPU_MACH_R600_CAYMAN`` 16 ``cayman``
|
||||
*reserved* 17-31 Reserved for ``r600``
|
||||
architecture processors.
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX600`` 32 ``gfx600``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX601`` 33 ``gfx601``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX700`` 34 ``gfx700``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX701`` 35 ``gfx701``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX702`` 36 ``gfx702``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX703`` 37 ``gfx703``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX800`` 38 ``gfx800``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX801`` 39 ``gfx801``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX802`` 40 ``gfx802``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX803`` 41 ``gfx803``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX810`` 42 ``gfx810``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX900`` 43 ``gfx900``
|
||||
``EF_AMDGPU_MACH_AMDGCN_GFX902`` 44 ``gfx902``
|
||||
================================= ========== =============================
|
||||
|
||||
Sections
|
||||
--------
|
||||
@ -515,11 +624,11 @@ if needed.
|
||||
Note Records
|
||||
------------
|
||||
|
||||
As required by ``ELFCLASS64``, minimal zero byte padding must be generated after
|
||||
the ``name`` field to ensure the ``desc`` field is 4 byte aligned. In addition,
|
||||
minimal zero byte padding must be generated to ensure the ``desc`` field size is
|
||||
a multiple of 4 bytes. The ``sh_addralign`` field of the ``.note`` section must
|
||||
be at least 4 to indicate at least 8 byte alignment.
|
||||
As required by ``ELFCLASS32`` and ``ELFCLASS64``, minimal zero byte padding must
|
||||
be generated after the ``name`` field to ensure the ``desc`` field is 4 byte
|
||||
aligned. In addition, minimal zero byte padding must be generated to ensure the
|
||||
``desc`` field size is a multiple of 4 bytes. The ``sh_addralign`` field of the
|
||||
``.note`` section must be at least 4 to indicate at least 8 byte alignment.
|
||||
|
||||
The AMDGPU backend code object uses the following ELF note records in the
|
||||
``.note`` section. The *Description* column specifies the layout of the note
|
||||
@ -537,7 +646,6 @@ Additional note records can be present.
|
||||
Name Type Description
|
||||
===== ============================== ======================================
|
||||
"AMD" ``NT_AMD_AMDGPU_HSA_METADATA`` <metadata null terminated string>
|
||||
"AMD" ``NT_AMD_AMDGPU_ISA`` <isa name null terminated string>
|
||||
===== ============================== ======================================
|
||||
|
||||
..
|
||||
@ -550,49 +658,9 @@ Additional note records can be present.
|
||||
============================== =====
|
||||
*reserved* 0-9
|
||||
``NT_AMD_AMDGPU_HSA_METADATA`` 10
|
||||
``NT_AMD_AMDGPU_ISA`` 11
|
||||
*reserved* 11
|
||||
============================== =====
|
||||
|
||||
``NT_AMD_AMDGPU_ISA``
|
||||
Specifies the instruction set architecture used by the machine code contained
|
||||
in the code object.
|
||||
|
||||
This note record is required for code objects containing machine code for
|
||||
processors matching the ``amdgcn`` architecture in table
|
||||
:ref:`amdgpu-processors`.
|
||||
|
||||
The null terminated string has the following syntax:
|
||||
|
||||
*architecture*\ ``-``\ *vendor*\ ``-``\ *os*\ ``-``\ *environment*\ ``-``\ *processor*
|
||||
|
||||
where:
|
||||
|
||||
*architecture*
|
||||
The architecture from table :ref:`amdgpu-target-triples-table`.
|
||||
|
||||
This is always ``amdgcn`` when the target triple OS is ``amdhsa`` (see
|
||||
:ref:`amdgpu-target-triples`).
|
||||
|
||||
*vendor*
|
||||
The vendor from table :ref:`amdgpu-target-triples-table`.
|
||||
|
||||
For the AMDGPU backend this is always ``amd``.
|
||||
|
||||
*os*
|
||||
The OS from table :ref:`amdgpu-target-triples-table`.
|
||||
|
||||
*environment*
|
||||
An environment from table :ref:`amdgpu-target-triples-table`, or blank if
|
||||
the environment has no affect on the execution of the code object.
|
||||
|
||||
For the AMDGPU backend this is currently always blank.
|
||||
*processor*
|
||||
The processor from table :ref:`amdgpu-processors-table`.
|
||||
|
||||
For example:
|
||||
|
||||
``amdgcn-amd-amdhsa--gfx901``
|
||||
|
||||
``NT_AMD_AMDGPU_HSA_METADATA``
|
||||
Specifies extensible metadata associated with the code objects executed on HSA
|
||||
[HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. It is required when
|
||||
@ -904,10 +972,6 @@ non-AMD key names should be prefixed by "*vendor-name*.".
|
||||
the kernel code. See
|
||||
:ref:`amdgpu-amdhsa-code-object-kernel-code-properties-metadata-mapping-table`
|
||||
for the mapping definition.
|
||||
"DebugProps" mapping Mapping of properties related to
|
||||
the kernel debugging. See
|
||||
:ref:`amdgpu-amdhsa-code-object-kernel-debug-properties-metadata-mapping-table`
|
||||
for the mapping definition.
|
||||
================= ============== ========= ================================
|
||||
|
||||
..
|
||||
@ -1175,9 +1239,9 @@ non-AMD key names should be prefixed by "*vendor-name*.".
|
||||
private address space
|
||||
memory required for a
|
||||
work-item in
|
||||
bytes. If
|
||||
IsDynamicCallstack
|
||||
is 1 then additional
|
||||
bytes. If the kernel
|
||||
uses a dynamic call
|
||||
stack then additional
|
||||
space must be added
|
||||
to this value for the
|
||||
call stack.
|
||||
@ -1188,7 +1252,7 @@ non-AMD key names should be prefixed by "*vendor-name*.".
|
||||
be a power of 2.
|
||||
"WavefrontSize" integer Required Wavefront size. Must
|
||||
be a power of 2.
|
||||
"NumSGPRs" integer Number of scalar
|
||||
"NumSGPRs" integer Required Number of scalar
|
||||
registers used by a
|
||||
wavefront for
|
||||
GFX6-GFX9. This
|
||||
@ -1204,44 +1268,37 @@ non-AMD key names should be prefixed by "*vendor-name*.".
|
||||
rounded up to the
|
||||
allocation
|
||||
granularity.
|
||||
"NumVGPRs" integer Number of vector
|
||||
"NumVGPRs" integer Required Number of vector
|
||||
registers used by
|
||||
each work-item for
|
||||
GFX6-GFX9
|
||||
"MaxFlatWorkGroupSize" integer Maximum flat
|
||||
"MaxFlatWorkGroupSize" integer Required Maximum flat
|
||||
work-group size
|
||||
supported by the
|
||||
kernel in work-items.
|
||||
"IsDynamicCallStack" boolean Indicates if the
|
||||
generated machine
|
||||
code is using a
|
||||
dynamically sized
|
||||
call stack.
|
||||
Must be >=1 and
|
||||
consistent with any
|
||||
non-0 values in
|
||||
FixedWorkGroupSize.
|
||||
"FixedWorkGroupSize" sequence of Corresponds to the
|
||||
3 integers dispatch work-group
|
||||
size X, Y, Z. If
|
||||
omitted, defaults to
|
||||
0, 0, 0. If an
|
||||
element is non-0 then
|
||||
the kernel must only
|
||||
be launched with a
|
||||
matching corresponding
|
||||
work-group size.
|
||||
"IsXNACKEnabled" boolean Indicates if the
|
||||
generated machine
|
||||
code is capable of
|
||||
supporting XNACK.
|
||||
supporting XNACK. See
|
||||
:ref:`amdgpu-target-features`.
|
||||
============================ ============== ========= =====================
|
||||
|
||||
..
|
||||
|
||||
.. table:: AMDHSA Code Object Kernel Debug Properties Metadata Mapping
|
||||
:name: amdgpu-amdhsa-code-object-kernel-debug-properties-metadata-mapping-table
|
||||
|
||||
=================================== ============== ========= ==============
|
||||
String Key Value Type Required? Description
|
||||
=================================== ============== ========= ==============
|
||||
"DebuggerABIVersion" sequence of
|
||||
2 integers
|
||||
"ReservedNumVGPRs" integer
|
||||
"ReservedFirstVGPR" integer
|
||||
"PrivateSegmentBufferSGPR" integer
|
||||
"WavefrontPrivateSegmentOffsetSGPR" integer
|
||||
=================================== ============== ========= ==============
|
||||
|
||||
.. TODO
|
||||
Plan to remove the debug properties metadata.
|
||||
|
||||
Kernel Dispatch
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
@ -1451,17 +1508,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
then additional space must
|
||||
be added to this value for
|
||||
the call stack.
|
||||
95:64 4 bytes MaxFlatWorkGroupSize Maximum flat work-group
|
||||
size supported by the
|
||||
kernel in work-items.
|
||||
96 1 bit IsDynamicCallStack Indicates if the generated
|
||||
machine code is using a
|
||||
dynamically sized call
|
||||
stack.
|
||||
97 1 bit IsXNACKEnabled Indicates if the generated
|
||||
machine code is capable of
|
||||
suppoting XNACK.
|
||||
127:98 30 bits Reserved, must be 0.
|
||||
127:64 8 bytes Reserved, must be 0.
|
||||
191:128 8 bytes KernelCodeEntryByteOffset Byte offset (possibly
|
||||
negative) from base
|
||||
address of kernel
|
||||
@ -1469,7 +1516,30 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
entry point instruction
|
||||
which must be 256 byte
|
||||
aligned.
|
||||
383:192 24 Reserved, must be 0.
|
||||
223:192 4 bytes MaxFlatWorkGroupSize Maximum flat work-group
|
||||
size supported by the
|
||||
kernel in work-items. If
|
||||
an exact work-group size
|
||||
is required then must be
|
||||
omitted or 0 and
|
||||
ReqdWorkGroupSize* must
|
||||
be set to non-0.
|
||||
239:224 2 bytes ReqdWorkGroupSizeX If present and non-0 then
|
||||
the kernel
|
||||
must be executed with the
|
||||
specified work-group size
|
||||
for X.
|
||||
255:240 2 bytes ReqdWorkGroupSizeY If present and non-0 then
|
||||
the kernel
|
||||
must be executed with the
|
||||
specified work-group size
|
||||
for Y.
|
||||
271:256 2 bytes ReqdWorkGroupSizeZ If present and non-0 then
|
||||
the kernel
|
||||
must be executed with the
|
||||
specified work-group size
|
||||
for Z.
|
||||
383:271 14 Reserved, must be 0.
|
||||
bytes
|
||||
415:384 4 bytes ComputePgmRsrc1 Compute Shader (CS)
|
||||
program settings used by
|
||||
@ -1509,7 +1579,10 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
should always be 0.
|
||||
457 1 bit EnableSGPRGridWorkgroupCountZ Not implemented in CP and
|
||||
should always be 0.
|
||||
463:458 6 bits Reserved, must be 0.
|
||||
462:458 5 bits Reserved, must be 0.
|
||||
463 1 bit IsXNACKEnabled Indicates if the generated
|
||||
machine code is capable of
|
||||
supporting XNACK.
|
||||
511:464 6 Reserved, must be 0.
|
||||
bytes
|
||||
512 **Total size 64 bytes.**
|
||||
@ -1528,7 +1601,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
granularity is device
|
||||
specific:
|
||||
|
||||
GFX6-9
|
||||
GFX6-GFX9
|
||||
- max_vgpr 1..256
|
||||
- roundup((max_vgpg + 1)
|
||||
/ 4) - 1
|
||||
@ -1540,7 +1613,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
granularity is device
|
||||
specific:
|
||||
|
||||
GFX6-8
|
||||
GFX6-GFX8
|
||||
- max_sgpr 1..112
|
||||
- roundup((max_sgpg + 1)
|
||||
/ 8) - 1
|
||||
@ -1679,7 +1752,7 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
|
||||
CP is responsible for
|
||||
filling in
|
||||
``COMPUTE_PGM_RSRC1.CDBG_USER``.
|
||||
26 1 bit FP16_OVFL GFX6-8
|
||||
26 1 bit FP16_OVFL GFX6-GFX8
|
||||
Reserved, must be 0.
|
||||
GFX9
|
||||
Wavefront starts execution
|
||||
@ -2166,7 +2239,7 @@ Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
|
||||
value to the hardware required SGPRn-3 and SGPRn-4 respectively.
|
||||
|
||||
The global segment can be accessed either using buffer instructions (GFX6 which
|
||||
has V# 64 bit address support), flat instructions (GFX7-9), or global
|
||||
has V# 64 bit address support), flat instructions (GFX7-GFX9), or global
|
||||
instructions (GFX9).
|
||||
|
||||
If buffer operations are used then the compiler can generate a V# with the
|
||||
@ -2212,7 +2285,7 @@ Offset SGPR registers (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`):
|
||||
GFX6
|
||||
Flat scratch is not supported.
|
||||
|
||||
GFX7-8
|
||||
GFX7-GFX8
|
||||
1. The low word of Flat Scratch Init is 32 bit byte offset from
|
||||
``SH_HIDDEN_PRIVATE_BASE_VIMID`` to the base of scratch backing memory
|
||||
being managed by SPI for the queue executing the kernel dispatch. This is
|
||||
@ -2305,7 +2378,7 @@ For GFX6-GFX9:
|
||||
same wavefront.
|
||||
* The vector memory operations are performed as wavefront wide operations and
|
||||
completion is reported to a wavefront in execution order. The exception is
|
||||
that for GFX7-9 ``flat_load/store/atomic`` instructions can report out of
|
||||
that for GFX7-GFX9 ``flat_load/store/atomic`` instructions can report out of
|
||||
vector memory order if they access LDS memory, and out of LDS operation order
|
||||
if they access global memory.
|
||||
* The vector memory operations access a single vector L1 cache shared by all
|
||||
@ -2332,7 +2405,7 @@ For GFX6-GFX9:
|
||||
* The L2 cache can be kept coherent with other agents on some targets, or ranges
|
||||
of virtual addresses can be set up to bypass it to ensure system coherence.
|
||||
|
||||
Private address space uses ``buffer_load/store`` using the scratch V# (GFX6-8),
|
||||
Private address space uses ``buffer_load/store`` using the scratch V# (GFX6-GFX8),
|
||||
or ``scratch_load/store`` (GFX9). Since only a single thread is accessing the
|
||||
memory, atomic memory orderings are not meaningful and all accesses are treated
|
||||
as non-atomic.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user