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Code Issues Projects Releases Wiki Activity

AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo

Browse Source 
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D16862

llvm-svn: 259900
This commit is contained in:
Tom Stellard 2016-02-05 18:44:57 +00:00
parent 9f8aefe66d
commit 350a5c65b3
5 changed files with 28 additions and 96 deletions
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30
lib/Target/AMDGPU/AMDGPUInstrInfo.h
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@ -73,35 +73,11 @@ public:
// Pure virtual funtions to be implemented by sub-classes.
//===---------------------------------------------------------------------===//
/// \brief Calculate the "Indirect Address" for the given \p RegIndex and
/// \p Channel
///
/// We model indirect addressing using a virtual address space that can be
/// accesed with loads and stores. The "Indirect Address" is the memory
/// address in this virtual address space that maps to the given \p RegIndex
/// and \p Channel.
virtual unsigned calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const = 0;
/// \returns The register class to be used for loading and storing values
/// from an "Indirect Address" .
virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
/// \brief Build instruction(s) for an indirect register write.
///
/// \returns The instruction that performs the indirect register write
virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const = 0;
/// \brief Build instruction(s) for an indirect register read.
///
/// \returns The instruction that performs the indirect register read
virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const = 0;
virtual const TargetRegisterClass *getIndirectAddrRegClass() const {
llvm_unreachable("getIndirectAddrRegClass() not implemented");
}
/// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
/// equivalent opcode that writes \p Channels Channels.

13
lib/Target/AMDGPU/R600InstrInfo.cpp
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@ -1047,6 +1047,12 @@ unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
return 2;
}
unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const {
assert(Channel == 0);
return RegIndex;
}
bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
switch(MI->getOpcode()) {
@ -1135,13 +1141,6 @@ void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
}
}
unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const {
// XXX: Remove when we support a stack width > 2
assert(Channel == 0);
return RegIndex;
}
const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
return &AMDGPU::R600_TReg32_XRegClass;
}

21
lib/Target/AMDGPU/R600InstrInfo.h
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@ -214,20 +214,33 @@ namespace llvm {
void reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const;
unsigned calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const override;
/// Calculate the "Indirect Address" for the given \p RegIndex and
/// \p Channel
///
/// We model indirect addressing using a virtual address space that can be
/// accesed with loads and stores. The "Indirect Address" is the memory
/// address in this virtual address space that maps to the given \p RegIndex
/// and \p Channel.
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
const TargetRegisterClass *getIndirectAddrRegClass() const override;
/// \brief Build instruction(s) for an indirect register write.
///
/// \returns The instruction that performs the indirect register write
MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const override;
unsigned OffsetReg) const;
/// \brief Build instruction(s) for an indirect register read.
///
/// \returns The instruction that performs the indirect register read
MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const override;
unsigned OffsetReg) const;
unsigned getMaxAlusPerClause() const;

42
lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -2595,12 +2595,6 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
// Indirect addressing callbacks
//===----------------------------------------------------------------------===//
unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const {
assert(Channel == 0);
return RegIndex;
}
const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
return &AMDGPU::VGPR_32RegClass;
}
@ -2962,42 +2956,6 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
return SGPRReg;
}
MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg,
unsigned Address, unsigned OffsetReg) const {
const DebugLoc &DL = MBB->findDebugLoc(I);
unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
getIndirectIndexBegin(*MBB->getParent()));
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
.addReg(IndirectBaseReg, RegState::Define)
.addOperand(I->getOperand(0))
.addReg(IndirectBaseReg)
.addReg(OffsetReg)
.addImm(0)
.addReg(ValueReg);
}
MachineInstrBuilder SIInstrInfo::buildIndirectRead(
MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg,
unsigned Address, unsigned OffsetReg) const {
const DebugLoc &DL = MBB->findDebugLoc(I);
unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
getIndirectIndexBegin(*MBB->getParent()));
return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
.addOperand(I->getOperand(0))
.addOperand(I->getOperand(1))
.addReg(IndirectBaseReg)
.addReg(OffsetReg)
.addImm(0);
}
void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const {
int End = getIndirectIndexEnd(MF);

14
lib/Target/AMDGPU/SIInstrInfo.h
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@ -414,22 +414,8 @@ public:
/// VALU if necessary.
void moveToVALU(MachineInstr &MI) const;
unsigned calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const override;
const TargetRegisterClass *getIndirectAddrRegClass() const override;
MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg,
unsigned Address,
unsigned OffsetReg) const override;
MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned ValueReg,
unsigned Address,
unsigned OffsetReg) const override;
void reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const;