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[Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
llvm-svn: 228708
This commit is contained in:
Colin LeMahieu
parent
7f0e9478f6
commit
350f7188f4
@ -51,6 +51,8 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, void const *Decoder);
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static const uint16_t IntRegDecoderTable[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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@ -105,6 +107,30 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/, void const *Decoder) {
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static const uint16_t CtrlReg64DecoderTable[] = {
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Hexagon::C1_0, Hexagon::NoRegister,
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Hexagon::C3_2, Hexagon::NoRegister,
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Hexagon::NoRegister, Hexagon::NoRegister,
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Hexagon::C7_6, Hexagon::NoRegister,
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Hexagon::C9_8, Hexagon::NoRegister,
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Hexagon::C11_10, Hexagon::NoRegister,
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Hexagon::CS, Hexagon::NoRegister,
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Hexagon::UPC, Hexagon::NoRegister
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};
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if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
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return MCDisassembler::Fail;
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if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
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return MCDisassembler::Fail;
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unsigned Register = CtrlReg64DecoderTable[RegNo];
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Inst.addOperand(MCOperand::CreateReg(Register));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/, const void *Decoder) {
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unsigned Register = 0;
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@ -1707,6 +1707,37 @@ let accessSize = WordAccess, opExtentAlign = 2 in {
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def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
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}
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let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0,
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opExtendable = 3, isExtentSigned = 1 in
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class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp>
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: LDInst<(outs DoubleRegs:$dst),
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(ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
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"$dst = "#str#"($src2 + #$offset)", [],
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"$src1 = $dst">, AddrModeRel {
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bits<4> name;
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bits<5> dst;
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bits<5> src2;
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bits<12> offset;
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bits<11> offsetBits;
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let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1},
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/* s11_0Ext */ offset{10-0});
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let IClass = 0b1001;
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let Inst{27} = 0b0;
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let Inst{26-25} = offsetBits{10-9};
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13-5} = offsetBits{8-0};
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let Inst{4-0} = dst;
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}
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let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
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def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
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let accessSize = ByteAccess, opExtentBits = 11 in
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def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
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// Patterns to select load-indexed (i.e. load from base+offset).
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multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
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InstHexagon MI> {
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@ -1872,6 +1903,41 @@ let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
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def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
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}
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//===----------------------------------------------------------------------===//
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// Template class for post increment fifo loads with immediate offset.
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, addrMode = PostInc in
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class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp >
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: LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
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(ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
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"$dst = "#mnemonic#"($src2++#$offset)" ,
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[], "$src2 = $dst2, $src1 = $dst" > ,
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PredNewRel {
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bits<5> dst;
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bits<5> src2;
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bits<5> offset;
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bits<4> offsetBits;
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let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0});
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let IClass = 0b1001;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13-12} = 0b00;
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let Inst{8-5} = offsetBits;
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let Inst{4-0} = dst;
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}
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// Ryy=memh_fifo(Rx++#s4:1)
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// Ryy=memb_fifo(Rx++#s4:0)
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let accessSize = ByteAccess in
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def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
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let accessSize = HalfWordAccess, opExtentAlign = 1 in
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def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>;
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//===----------------------------------------------------------------------===//
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// Template class for post increment loads with register offset.
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//===----------------------------------------------------------------------===//
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@ -1976,6 +2042,33 @@ let accessSize = WordAccess in {
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let accessSize = DoubleWordAccess in
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def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
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// Load / Post increment circular addressing mode.
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let Uses = [CS], hasSideEffects = 0 in
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class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
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: LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
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(ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
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"$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
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"$Rz = $_dst_, $dst = $_src_" > {
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bits<5> dst;
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bits<5> Rz;
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bit Mu;
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let accessSize = AccessSz;
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let IClass = 0b1001;
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let Inst{27-25} = 0b100;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = Rz;
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let Inst{13} = Mu;
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let Inst{12} = 0b0;
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let Inst{9} = 0b1;
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let Inst{7} = 0b0;
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let Inst{4-0} = dst;
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}
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def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
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def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
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//===----------------------------------------------------------------------===//
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// Circular loads with immediate offset.
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//===----------------------------------------------------------------------===//
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@ -2035,6 +2128,37 @@ let accessSize = WordAccess, hasNewValue = 0 in {
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let accessSize = DoubleWordAccess, hasNewValue = 0 in
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def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
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//===----------------------------------------------------------------------===//
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// Circular loads - Pseudo
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//
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// Please note that the input operand order in the pseudo instructions
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// doesn't match with the real instructions. Pseudo instructions operand
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// order should mimics the ordering in the intrinsics. Also, 'src2' doesn't
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// appear in the AsmString because it's same as 'dst'.
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
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class T_load_pci_pseudo <string opc, RegisterClass RC>
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: LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
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".error \"$dst = "#opc#"($src1++#$src4:circ($src3))\"",
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[], "$src1 = $_dst_">;
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def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
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def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
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def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
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def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
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def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
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def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>;
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// TODO: memb_fifo and memh_fifo must take destination register as input.
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// One-off circ loads - not enough in common to break into a class.
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let accessSize = ByteAccess in
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def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
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let accessSize = HalfWordAccess, opExtentAlign = 1 in
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def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>;
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// L[24]_load[wd]_locked: Load word/double with lock.
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let isSoloAX = 1 in
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class T_load_locked <string mnemonic, RegisterClass RC>
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@ -2122,6 +2246,30 @@ def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
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def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
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def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
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def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
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def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs,
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HalfWordAccess, 0b0010>;
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//===----------------------------------------------------------------------===//
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// Bit-reversed loads - Pseudo
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//
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// Please note that 'src2' doesn't appear in the AsmString because
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// it's same as 'dst'.
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
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class T_load_pbr_pseudo <string opc, RegisterClass RC>
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: LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
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".error \"$dst = "#opc#"($src1++$src3:brev)\"",
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[], "$src1 = $_dst_">;
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def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
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def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
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def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
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def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
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def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
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def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>;
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//===----------------------------------------------------------------------===//
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// LD -
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//===----------------------------------------------------------------------===//
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@ -3548,6 +3696,26 @@ def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
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def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
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def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
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//===----------------------------------------------------------------------===//
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// Circular stores - Pseudo
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//
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// Please note that the input operand order in the pseudo instructions
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// doesn't match with the real instructions. Pseudo instructions operand
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// order should mimics the ordering in the intrinsics.
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
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class T_store_pci_pseudo <string opc, RegisterClass RC>
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: STInstPI<(outs IntRegs:$_dst_),
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(ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
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".error \""#opc#"($src1++#$src4:circ($src3)) = $src2\"",
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[], "$_dst_ = $src1">;
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def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
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def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
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def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
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def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
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def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>;
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//===----------------------------------------------------------------------===//
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// Circular stores with auto-increment register
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//===----------------------------------------------------------------------===//
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@ -3691,6 +3859,26 @@ def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
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let BaseOpcode = "S2_storeri_pbr" in
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def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
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//===----------------------------------------------------------------------===//
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// Bit-reversed stores - Pseudo
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//
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// Please note that the input operand order in the pseudo instructions
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// doesn't match with the real instructions. Pseudo instructions operand
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// order should mimics the ordering in the intrinsics.
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//===----------------------------------------------------------------------===//
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let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
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class T_store_pbr_pseudo <string opc, RegisterClass RC>
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: STInstPI<(outs IntRegs:$_dst_),
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(ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
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".error \""#opc#"($src1++$src3:brev) = $src2\"",
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[], "$_dst_ = $src1">;
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def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
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def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
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def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
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def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
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def S2_storerd_pbr_pseudo : T_store_pbr_pseudo <"memd", DoubleRegs>;
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//===----------------------------------------------------------------------===//
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// ST -
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//===----------------------------------------------------------------------===//
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@ -3870,6 +4058,10 @@ def S2_asr_i_r_rnd_goodsyntax
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"$dst = asrrnd($src, #$u5)",
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[], "", S_2op_tc_1_SLOT23>;
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let isAsmParserOnly = 1 in
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def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
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"$dst = not($src)">;
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def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
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(i32 1))),
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(i32 1))),
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@ -3914,6 +4106,9 @@ def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
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def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
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def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
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def : Pat<(not (i64 DoubleRegs:$src1)),
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(A2_notp DoubleRegs:$src1)>;
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//===----------------------------------------------------------------------===//
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// STYPE/BIT +
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//===----------------------------------------------------------------------===//
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@ -4161,6 +4356,27 @@ def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
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let Inst{1-0} = Pd;
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}
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let hasSideEffects = 0, isCodeGenOnly = 1 in
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def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
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"$dst = $src">;
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// Patterns for loads of i1:
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def: Pat<(i1 (load AddrFI:$fi)),
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(C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
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def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s11_0ExtPred:$Off))),
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(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
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def: Pat<(i1 (load (i32 IntRegs:$Rs))),
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(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
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def I1toI32: OutPatFrag<(ops node:$Rs),
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(C2_muxii (i1 $Rs), 1, 0)>;
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def I32toI1: OutPatFrag<(ops node:$Rs),
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(i1 (C2_tfrrp (i32 $Rs)))>;
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defm: Storexm_pat<store, I1, s11_0ExtPred, I1toI32, S2_storerb_io>;
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def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
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//===----------------------------------------------------------------------===//
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// STYPE/PRED -
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@ -4423,6 +4639,7 @@ class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
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}
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def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
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def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>;
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def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
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def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
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@ -4444,6 +4661,7 @@ class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
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let hasNewValue = 1, opNewValue = 0 in
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def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
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def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>;
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def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
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def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
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@ -4603,9 +4821,14 @@ def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
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"$dst = CONST64(#$global)",
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[(set (i64 DoubleRegs:$dst), imm:$global)]>;
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let isCodeGenOnly = 1 in
|
||||
def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
|
||||
"$dst = xor($dst, $dst)",
|
||||
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
|
||||
isCodeGenOnly = 1 in
|
||||
def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "",
|
||||
[(set (i1 PredRegs:$dst), 1)]>;
|
||||
|
||||
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
|
||||
isCodeGenOnly = 1 in
|
||||
def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)",
|
||||
[(set (i1 PredRegs:$dst), 0)]>;
|
||||
|
||||
// Pseudo instructions.
|
||||
|
||||
@ -3863,6 +3863,13 @@ def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
|
||||
def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
|
||||
def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
|
||||
|
||||
// Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd
|
||||
def: Loadam_pat<load, i1, addrga, I32toI1, L4_loadrub_abs>;
|
||||
def: Loadam_pat<load, i1, addrgp, I32toI1, L2_loadrubgp>;
|
||||
|
||||
def: Stoream_pat<store, I1, addrga, I1toI32, S2_storerbabs>;
|
||||
def: Stoream_pat<store, I1, addrgp, I1toI32, S2_storerbgp>;
|
||||
|
||||
// Map from load(globaladdress) -> mem[u][bhwd](#foo)
|
||||
class LoadGP_pats <PatFrag ldOp, InstHexagon MI, ValueType VT = i32>
|
||||
: Pat <(VT (ldOp (HexagonCONST32_GP tglobaladdr:$global))),
|
||||
@ -3887,6 +3894,11 @@ let AddedComplexity = 100 in {
|
||||
def: LoadGP_pats <zextloadi1, L2_loadrubgp>;
|
||||
}
|
||||
|
||||
// Transfer global address into a register
|
||||
def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
|
||||
def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
|
||||
def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
|
||||
|
||||
|
||||
@ -144,6 +144,8 @@ defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
|
||||
|
||||
defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
|
||||
defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
|
||||
def: Storex_simple_pat<store, F32, S2_storeri_io>;
|
||||
def: Storex_simple_pat<store, F64, S2_storerd_io>;
|
||||
|
||||
let isFP = 1, hasNewValue = 1, opNewValue = 0 in
|
||||
class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
|
||||
@ -188,6 +190,24 @@ let Itinerary = M_tc_3x_SLOT23 in {
|
||||
def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 100, Predicates = [HasV5T] in {
|
||||
def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
|
||||
F32:$src1, F32:$src2)),
|
||||
(F2_sfmin F32:$src1, F32:$src2)>;
|
||||
|
||||
def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
|
||||
F32:$src2, F32:$src1)),
|
||||
(F2_sfmin F32:$src1, F32:$src2)>;
|
||||
|
||||
def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
|
||||
F32:$src1, F32:$src2)),
|
||||
(F2_sfmax F32:$src1, F32:$src2)>;
|
||||
|
||||
def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
|
||||
F32:$src2, F32:$src1)),
|
||||
(F2_sfmax F32:$src1, F32:$src2)>;
|
||||
}
|
||||
|
||||
def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
|
||||
def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
|
||||
|
||||
@ -699,6 +719,9 @@ def F2_sffms: T_sfmpy_acc <1, 0>;
|
||||
def F2_sffma_lib: T_sfmpy_acc <0, 1>;
|
||||
def F2_sffms_lib: T_sfmpy_acc <1, 1>;
|
||||
|
||||
def : Pat <(f32 (fma F32:$src2, F32:$src3, F32:$src1)),
|
||||
(F2_sffma F32:$src1, F32:$src2, F32:$src3)>;
|
||||
|
||||
// Floating-point fused multiply add w/ additional scaling (2**pu).
|
||||
let isFP = 1, hasNewValue = 1 in
|
||||
def F2_sffma_sc: MInst <
|
||||
@ -739,6 +762,38 @@ def MUX_ri_f : ALU32_rr<(outs IntRegs:$dst),
|
||||
[(set F32:$dst, (f32 (select I1:$src1, fpimm:$src2, F32:$src3)))]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def: Pat<(select I1:$src1, F32:$src2, F32:$src3),
|
||||
(C2_mux I1:$src1, F32:$src2, F32:$src3)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def: Pat<(select (i1 (setult F32:$src1, F32:$src2)), F32:$src3, F32:$src4),
|
||||
(C2_mux (F2_sfcmpgt F32:$src2, F32:$src1), F32:$src4, F32:$src3)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def: Pat<(select I1:$src1, F64:$src2, F64:$src3),
|
||||
(C2_vmux I1:$src1, F64:$src2, F64:$src3)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def: Pat<(select (i1 (setult F64:$src1, F64:$src2)), F64:$src3, F64:$src4),
|
||||
(C2_vmux (F2_dfcmpgt F64:$src2, F64:$src1), F64:$src3, F64:$src4)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
|
||||
// => r0 = MUX_ir_f(p0, #i, r1)
|
||||
def: Pat<(select (not I1:$src1), fpimm:$src2, F32:$src3),
|
||||
(MUX_ir_f I1:$src1, F32:$src3, fpimm:$src2)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
|
||||
// => r0 = MUX_ri_f(p0, r1, #i)
|
||||
def: Pat<(select (not I1:$src1), F32:$src2, fpimm:$src3),
|
||||
(MUX_ri_f I1:$src1, fpimm:$src3, F32:$src2)>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def: Pat<(i32 (fp_to_sint F64:$src1)),
|
||||
(LoReg (F2_conv_df2d_chop F64:$src1))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// :natural forms of vasrh and vasrhub insns
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -849,7 +904,6 @@ def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
|
||||
}
|
||||
|
||||
// Instructions to create floating point constant
|
||||
let hasNewValue = 1, opNewValue = 0 in
|
||||
class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
|
||||
: ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
|
||||
"$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user