RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity

Remove the code that emits MIPS' .cprestore directive.

Browse Source 
llvm-svn: 157493
This commit is contained in:
Akira Hatanaka 2012-05-25 20:42:55 +00:00
parent 40236c8d6c
commit 3514125a37
3 changed files with 0 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -112,28 +112,6 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
return; return;
} }
case Mips::CPRESTORE: {
const MachineOperand &MO = MI->getOperand(0);
assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
int64_t Offset = MO.getImm();
if (OutStreamer.hasRawTextSupport()) {
if (!isInt<16>(Offset)) {
EmitInstrWithMacroNoAT(MI);
return;
}
} else {
MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
I != MCInsts.end(); ++I)
OutStreamer.EmitInstruction(*I);
return;
}
break;
}
default: default:
break; break;
} }

27
lib/Target/Mips/MipsMCInstLower.cpp
View File

@ -140,33 +140,6 @@ void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg); CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
} }
// Lower ".cprestore offset" to "sw $gp, offset($sp)".
void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
SmallVector<MCInst, 4>& MCInsts) {
assert(isInt<32>(Offset) && (Offset >= 0) &&
"Imm operand of .cprestore must be a non-negative 32-bit value.");
MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
if (!isInt<16>(Offset)) {
unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
Offset &= 0xffff;
MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
BaseReg = ATReg;
// lui at,hi
// addu at,at,sp
MCInsts.resize(2);
CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
}
MCInst Sw;
CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
MCInsts.push_back(Sw);
}
MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO, MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
unsigned offset) const { unsigned offset) const {
MachineOperandType MOTy = MO.getType(); MachineOperandType MOTy = MO.getType();

1
lib/Target/Mips/MipsMCInstLower.h
View File

@ -34,7 +34,6 @@ public:
void Initialize(Mangler *mang, MCContext* C); void Initialize(Mangler *mang, MCContext* C);
void Lower(const MachineInstr *MI, MCInst &OutMI) const; void Lower(const MachineInstr *MI, MCInst &OutMI) const;
void LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts); void LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts);
void LowerCPRESTORE(int64_t Offset, SmallVector<MCInst, 4>& MCInsts);
void LowerUnalignedLoadStore(const MachineInstr *MI, void LowerUnalignedLoadStore(const MachineInstr *MI,
SmallVector<MCInst, 4>& MCInsts); SmallVector<MCInst, 4>& MCInsts);
void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts); void LowerSETGP01(SmallVector<MCInst, 4>& MCInsts);