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AMDGPU: Remove random TGSI intrinsic

I don't think this was ever used.

llvm-svn: 258514
This commit is contained in:
Matt Arsenault 2016-01-22 18:42:44 +00:00
parent 21c6e6f537
commit 351925633e
3 changed files with 0 additions and 14 deletions

View File

@ -73,9 +73,4 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
def int_AMDIL_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
}
let TargetPrefix = "TGSI", isTarget = 1 in {
def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[IntrNoMem]>;
}
include "SIIntrinsics.td"

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@ -356,8 +356,6 @@ let hasSideEffects = 1 in {
def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
}
def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
let Pattern = [];
let Itinerary = AnyALU;

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@ -1148,12 +1148,6 @@ def : Pat<
def : RcpPat<recip_ieee, f32>;
}
class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
: Pat <
(int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
(exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
>;
//===----------------------------------------------------------------------===//
// R600 / R700 Instructions
//===----------------------------------------------------------------------===//
@ -1192,7 +1186,6 @@ let Predicates = [isR600] in {
defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
def : RsqPat<RECIPSQRT_IEEE_r600, f32>;