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[SystemZ] Improve foldMemoryOperandImpl().
Swap the compare operands if LHS is spilled while updating the CCMask:s of the CC users. This is relatively straight forward since the live-in lists for the CC register can be assumed to be correct during register allocation (thanks to 659efa2). Also fold a spilled operand of an LOCR/SELR into an LOC(G). Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D67437
This commit is contained in:
Jonas Paulsson
parent
ed59983363
commit
354d615db9
@ -2190,15 +2190,6 @@ static bool shouldSwapCmpOperands(const Comparison &C) {
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return false;
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}
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// Return a version of comparison CC mask CCMask in which the LT and GT
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// actions are swapped.
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static unsigned reverseCCMask(unsigned CCMask) {
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return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
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(CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
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(CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
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(CCMask & SystemZ::CCMASK_CMP_UO));
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}
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// Check whether C tests for equality between X and Y and whether X - Y
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// or Y - X is also computed. In that case it's better to compare the
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// result of the subtraction against zero.
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@ -2234,7 +2225,7 @@ static void adjustForFNeg(Comparison &C) {
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SDNode *N = *I;
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if (N->getOpcode() == ISD::FNEG) {
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C.Op0 = SDValue(N, 0);
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C.CCMask = reverseCCMask(C.CCMask);
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C.CCMask = SystemZ::reverseCCMask(C.CCMask);
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return;
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}
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}
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@ -2601,7 +2592,7 @@ static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
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if (shouldSwapCmpOperands(C)) {
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std::swap(C.Op0, C.Op1);
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C.CCMask = reverseCCMask(C.CCMask);
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C.CCMask = SystemZ::reverseCCMask(C.CCMask);
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}
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adjustForTestUnderMask(DAG, DL, C);
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@ -6277,15 +6268,7 @@ static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask) {
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return false;
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// Compute the effective CC mask for the new branch or select.
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switch (CCMask) {
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case SystemZ::CCMASK_CMP_EQ: break;
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case SystemZ::CCMASK_CMP_NE: break;
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case SystemZ::CCMASK_CMP_LT: CCMask = SystemZ::CCMASK_CMP_GT; break;
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case SystemZ::CCMASK_CMP_GT: CCMask = SystemZ::CCMASK_CMP_LT; break;
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case SystemZ::CCMASK_CMP_LE: CCMask = SystemZ::CCMASK_CMP_GE; break;
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case SystemZ::CCMASK_CMP_GE: CCMask = SystemZ::CCMASK_CMP_LE; break;
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default: return false;
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}
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CCMask = SystemZ::reverseCCMask(CCMask);
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// Return the updated CCReg link.
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CCReg = IPM->getOperand(0);
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@ -2807,6 +2807,10 @@ class CondUnaryRSY<string mnemonic, bits<16> opcode,
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let mayLoad = 1;
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let AccessBytes = bytes;
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let CCMaskLast = 1;
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let OpKey = mnemonic#"r"#cls;
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let OpType = "mem";
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let MemKey = mnemonic#cls;
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let MemType = "target";
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}
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// Like CondUnaryRSY, but used for the raw assembly form. The condition-code
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@ -3211,6 +3215,8 @@ class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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let CCMaskLast = 1;
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let NumOpsKey = !subst("loc", "sel", mnemonic);
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let NumOpsValue = "2";
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let OpKey = mnemonic#cls1;
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let OpType = "reg";
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}
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// Like CondBinaryRRF, but used for the raw assembly form. The condition-code
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@ -3252,6 +3258,8 @@ class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
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let CCMaskLast = 1;
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let NumOpsKey = mnemonic;
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let NumOpsValue = "3";
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let OpKey = mnemonic#cls1;
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let OpType = "reg";
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}
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// Like CondBinaryRRFa, but used for the raw assembly form. The condition-code
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@ -4775,6 +4783,20 @@ class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
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let hasNoSchedulingInfo = 1;
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}
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// Same as MemFoldPseudo but for Load On Condition with CC operands.
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class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
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AddressingMode mode>
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: Pseudo<(outs cls:$R1),
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(ins cls:$R2, mode:$XBD2, cond4:$valid, cond4:$M3), []> {
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let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
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let OpType = "mem";
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let MemKey = mnemonic#cls;
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let MemType = "pseudo";
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let mayLoad = 1;
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let AccessBytes = bytes;
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let hasNoSchedulingInfo = 1;
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}
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// Like CompareRI, but expanded after RA depending on the choice of register.
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class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
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ImmOpWithPattern imm>
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@ -4813,6 +4835,8 @@ class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1,
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let CCMaskLast = 1;
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let NumOpsKey = !subst("loc", "sel", mnemonic);
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let NumOpsValue = "2";
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let OpKey = mnemonic#cls1;
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let OpType = "reg";
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}
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// Like CondBinaryRRFa, but expanded after RA depending on the choice of
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@ -4826,6 +4850,8 @@ class CondBinaryRRFaPseudo<string mnemonic, RegisterOperand cls1,
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let CCMaskLast = 1;
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let NumOpsKey = mnemonic;
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let NumOpsValue = "3";
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let OpKey = mnemonic#cls1;
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let OpType = "reg";
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}
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// Like CondBinaryRIE, but expanded after RA depending on the choice of
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@ -4842,8 +4868,9 @@ class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
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// Like CondUnaryRSY, but expanded after RA depending on the choice of
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// register.
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class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
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bits<5> bytes, AddressingMode mode = bdaddr20only>
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class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdaddr20only>
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: Pseudo<(outs cls:$R1),
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(ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
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[(set cls:$R1,
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@ -4854,6 +4881,10 @@ class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
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let mayLoad = 1;
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let AccessBytes = bytes;
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let CCMaskLast = 1;
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let OpKey = mnemonic#"r"#cls;
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let OpType = "mem";
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let MemKey = mnemonic#cls;
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let MemType = "target";
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}
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// Like CondStoreRSY, but expanded after RA depending on the choice of
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@ -5066,6 +5097,22 @@ multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode,
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def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>;
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}
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multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdaddr20only> {
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defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
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def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
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}
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multiclass CondUnaryRSYPseudoAndMemFold<string mnemonic,
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SDPatternOperator operator,
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RegisterOperand cls, bits<5> bytes,
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AddressingMode mode = bdaddr20only> {
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def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>;
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def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
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}
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// Define an instruction that operates on two fixed-length blocks of memory,
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// and associated pseudo instructions for operating on blocks of any size.
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// The Sequence form uses a straight-line sequence of instructions and
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@ -1150,14 +1150,31 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
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// commutable, try to change <INSN>R into <INSN>.
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unsigned NumOps = MI.getNumExplicitOperands();
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int MemOpcode = SystemZ::getMemOpcode(Opcode);
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if (MemOpcode == -1)
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return nullptr;
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// Try to swap compare operands if possible.
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bool NeedsCommute = false;
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if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
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MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR) &&
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OpNum == 0 && prepareCompareSwapOperands(MI))
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NeedsCommute = true;
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bool CCOperands = false;
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if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
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MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
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assert(MI.getNumOperands() == 6 && NumOps == 5 &&
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"LOCR/SELR instruction operands corrupt?");
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NumOps -= 2;
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CCOperands = true;
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}
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// See if this is a 3-address instruction that is convertible to 2-address
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// and suitable for folding below. Only try this with virtual registers
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// and a provided VRM (during regalloc).
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bool NeedsCommute = false;
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if (SystemZ::getTwoOperandOpcode(Opcode) != -1 && MemOpcode != -1) {
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if (SystemZ::getTwoOperandOpcode(Opcode) != -1) {
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if (VRM == nullptr)
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MemOpcode = -1;
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return nullptr;
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else {
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assert(NumOps == 3 && "Expected two source registers.");
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Register DstReg = MI.getOperand(0).getReg();
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@ -1172,11 +1189,10 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
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DstPhys == VRM->getPhys(SrcReg))
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NeedsCommute = (OpNum == 1);
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else
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MemOpcode = -1;
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return nullptr;
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}
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}
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if (MemOpcode >= 0) {
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if ((OpNum == NumOps - 1) || NeedsCommute) {
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const MCInstrDesc &MemDesc = get(MemOpcode);
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uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
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@ -1185,20 +1201,31 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
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uint64_t Offset = Size - AccessBytes;
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MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
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MI.getDebugLoc(), get(MemOpcode));
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if (MI.isCompare()) {
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assert(NumOps == 2 && "Expected 2 register operands for a compare.");
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MIB.add(MI.getOperand(NeedsCommute ? 1 : 0));
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}
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else {
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MIB.add(MI.getOperand(0));
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if (NeedsCommute)
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MIB.add(MI.getOperand(2));
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else
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for (unsigned I = 1; I < OpNum; ++I)
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MIB.add(MI.getOperand(I));
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}
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MIB.addFrameIndex(FrameIndex).addImm(Offset);
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if (MemDesc.TSFlags & SystemZII::HasIndex)
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MIB.addReg(0);
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if (CCOperands) {
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unsigned CCValid = MI.getOperand(NumOps).getImm();
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unsigned CCMask = MI.getOperand(NumOps + 1).getImm();
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MIB.addImm(CCValid);
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MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask);
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}
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transferDeadCC(&MI, MIB);
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transferMIFlag(&MI, MIB, MachineInstr::NoSWrap);
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return MIB;
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}
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}
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return nullptr;
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}
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@ -1706,6 +1733,56 @@ unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
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return 0;
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}
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bool SystemZInstrInfo::
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prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
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assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
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MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
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"Not a compare reg/reg.");
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MachineBasicBlock *MBB = MBBI->getParent();
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bool CCLive = true;
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SmallVector<MachineInstr *, 4> CCUsers;
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for (MachineBasicBlock::iterator Itr = std::next(MBBI);
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Itr != MBB->end(); ++Itr) {
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if (Itr->readsRegister(SystemZ::CC)) {
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unsigned Flags = Itr->getDesc().TSFlags;
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if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
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CCUsers.push_back(&*Itr);
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else
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return false;
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}
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if (Itr->definesRegister(SystemZ::CC)) {
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CCLive = false;
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break;
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}
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}
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if (CCLive) {
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LivePhysRegs LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
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LiveRegs.addLiveOuts(*MBB);
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if (LiveRegs.contains(SystemZ::CC))
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return false;
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}
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// Update all CC users.
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for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
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unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
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unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
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0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
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MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(FirstOpNum + 1);
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unsigned NewCCMask = SystemZ::reverseCCMask(CCMaskMO.getImm());
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CCMaskMO.setImm(NewCCMask);
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}
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return true;
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}
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unsigned SystemZ::reverseCCMask(unsigned CCMask) {
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return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
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(CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
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(CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
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(CCMask & SystemZ::CCMASK_CMP_UO));
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}
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unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
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if (!STI.hasLoadAndTrap())
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return 0;
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@ -155,6 +155,10 @@ enum FusedCompareType {
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namespace SystemZ {
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int getTwoOperandOpcode(uint16_t Opcode);
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int getTargetMemOpcode(uint16_t Opcode);
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// Return a version of comparison CC mask CCMask in which the LT and GT
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// actions are swapped.
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unsigned reverseCCMask(unsigned CCMask);
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}
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class SystemZInstrInfo : public SystemZGenInstrInfo {
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@ -314,6 +318,12 @@ public:
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SystemZII::FusedCompareType Type,
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const MachineInstr *MI = nullptr) const;
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// Try to find all CC users of the compare instruction (MBBI) and update
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// all of them to maintain equivalent behavior after swapping the compare
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// operands. Return false if not all users can be conclusively found and
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// handled. The compare instruction is *not* changed.
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bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const;
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// If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
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// operation exists, returh the opcode for the latter, otherwise return 0.
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unsigned getLoadAndTrap(unsigned Opcode) const;
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@ -492,7 +492,7 @@ let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in {
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let isCommutable = 1 in {
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// Expands to SELR or SELFHR or a branch-and-move sequence,
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// depending on the choice of registers.
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def SELRMux : CondBinaryRRFaPseudo<"selrmux", GRX32, GRX32, GRX32>;
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def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>;
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defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>;
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defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>;
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defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>;
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@ -525,13 +525,13 @@ let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
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let isCommutable = 1 in {
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// Expands to LOCR or LOCFHR or a branch-and-move sequence,
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// depending on the choice of registers.
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def LOCRMux : CondBinaryRRFPseudo<"locrmux", GRX32, GRX32>;
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def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>;
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defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>;
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}
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// Load on condition. Matched via DAG pattern.
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// Expands to LOC or LOCFH, depending on the choice of register.
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def LOCMux : CondUnaryRSYPseudo<simple_load, GRX32, 4>;
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defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>;
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defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>;
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// Store on condition. Expanded from CondStore* pseudos.
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@ -564,7 +564,7 @@ let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
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// Load on condition. Matched via DAG pattern.
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defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>;
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defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, simple_load, GR64, 8>;
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defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>;
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// Store on condition. Expanded from CondStore* pseudos.
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defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>;
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100
test/CodeGen/SystemZ/cond-move-10.ll
Normal file
100
test/CodeGen/SystemZ/cond-move-10.ll
Normal file
@ -0,0 +1,100 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
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;
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; Test that a reload of a LOCGR/SELGR operand can be folded into a LOC
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; instruction.
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declare i64 @foo()
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declare i32 @foo32()
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; Check that conditional loads of spilled values can use LOCG rather than LOCGR.
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define void @f0(i64 *%ptr0, i64 *%dstPtr) {
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; CHECK-LABEL: f0:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: locglh {{.*}} # 8-byte Folded Reload
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; CHECK: br %r14
|
||||
%ptr1 = getelementptr i64, i64 *%ptr0, i64 2
|
||||
%ptr2 = getelementptr i64, i64 *%ptr0, i64 4
|
||||
%ptr3 = getelementptr i64, i64 *%ptr0, i64 6
|
||||
%ptr4 = getelementptr i64, i64 *%ptr0, i64 8
|
||||
%ptr5 = getelementptr i64, i64 *%ptr0, i64 10
|
||||
%ptr6 = getelementptr i64, i64 *%ptr0, i64 12
|
||||
%ptr7 = getelementptr i64, i64 *%ptr0, i64 14
|
||||
%ptr8 = getelementptr i64, i64 *%ptr0, i64 16
|
||||
%ptr9 = getelementptr i64, i64 *%ptr0, i64 18
|
||||
|
||||
%val0 = load i64, i64 *%ptr0
|
||||
%val1 = load i64, i64 *%ptr1
|
||||
%val2 = load i64, i64 *%ptr2
|
||||
%val3 = load i64, i64 *%ptr3
|
||||
%val4 = load i64, i64 *%ptr4
|
||||
%val5 = load i64, i64 *%ptr5
|
||||
%val6 = load i64, i64 *%ptr6
|
||||
%val7 = load i64, i64 *%ptr7
|
||||
%val8 = load i64, i64 *%ptr8
|
||||
%val9 = load i64, i64 *%ptr9
|
||||
|
||||
%ret = call i64 @foo()
|
||||
|
||||
%add0 = add i64 %ret, %val0
|
||||
%add1 = add i64 %add0, %val1
|
||||
%add2 = add i64 %add1, %val2
|
||||
%add3 = add i64 %add2, %val3
|
||||
%add4 = add i64 %add3, %val4
|
||||
%add5 = add i64 %add4, %val5
|
||||
%add6 = add i64 %add5, %val6
|
||||
%add7 = add i64 %add6, %val7
|
||||
%add8 = add i64 %add7, %val8
|
||||
|
||||
%cond = icmp eq i64 %add7, %add8
|
||||
%res = select i1 %cond, i64 %add8, i64 %val9
|
||||
|
||||
store i64 %res, i64* %dstPtr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check that conditional loads of spilled values can use LOC rather than LOCR.
|
||||
define void @f1(i32 *%ptr0, i32 *%dstPtr) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: brasl %r14, foo32@PLT
|
||||
; CHECK: loclh {{.*}} # 4-byte Folded Reload
|
||||
; CHECK: br %r14
|
||||
%ptr1 = getelementptr i32, i32 *%ptr0, i32 2
|
||||
%ptr2 = getelementptr i32, i32 *%ptr0, i32 4
|
||||
%ptr3 = getelementptr i32, i32 *%ptr0, i32 6
|
||||
%ptr4 = getelementptr i32, i32 *%ptr0, i32 8
|
||||
%ptr5 = getelementptr i32, i32 *%ptr0, i32 10
|
||||
%ptr6 = getelementptr i32, i32 *%ptr0, i32 12
|
||||
%ptr7 = getelementptr i32, i32 *%ptr0, i32 14
|
||||
%ptr8 = getelementptr i32, i32 *%ptr0, i32 16
|
||||
%ptr9 = getelementptr i32, i32 *%ptr0, i32 18
|
||||
|
||||
%val0 = load i32, i32 *%ptr0
|
||||
%val1 = load i32, i32 *%ptr1
|
||||
%val2 = load i32, i32 *%ptr2
|
||||
%val3 = load i32, i32 *%ptr3
|
||||
%val4 = load i32, i32 *%ptr4
|
||||
%val5 = load i32, i32 *%ptr5
|
||||
%val6 = load i32, i32 *%ptr6
|
||||
%val7 = load i32, i32 *%ptr7
|
||||
%val8 = load i32, i32 *%ptr8
|
||||
%val9 = load i32, i32 *%ptr9
|
||||
|
||||
%ret = call i32 @foo32()
|
||||
|
||||
%add0 = add i32 %ret, %val0
|
||||
%add1 = add i32 %add0, %val1
|
||||
%add2 = add i32 %add1, %val2
|
||||
%add3 = add i32 %add2, %val3
|
||||
%add4 = add i32 %add3, %val4
|
||||
%add5 = add i32 %add4, %val5
|
||||
%add6 = add i32 %add5, %val6
|
||||
%add7 = add i32 %add6, %val7
|
||||
%add8 = add i32 %add7, %val8
|
||||
|
||||
%cond = icmp eq i32 %add7, %add8
|
||||
%res = select i1 %cond, i32 %add8, i32 %val9
|
||||
|
||||
store i32 %res, i32* %dstPtr
|
||||
ret void
|
||||
}
|
||||
323
test/CodeGen/SystemZ/int-cmp-56.mir
Normal file
323
test/CodeGen/SystemZ/int-cmp-56.mir
Normal file
@ -0,0 +1,323 @@
|
||||
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass greedy %s -o - \
|
||||
# RUN: | FileCheck %s
|
||||
#
|
||||
# Test that a reload can be folded into a compare instruction after swapping
|
||||
# operands (when the LHS register is spilled).
|
||||
|
||||
--- |
|
||||
declare i64 @foo()
|
||||
define i64 @fun1(i64* %ptr0) { ret i64 0 }
|
||||
define i64 @fun2(i64* %ptr0) { ret i64 0 }
|
||||
|
||||
declare i32 @foo32()
|
||||
define i32 @fun3(i32* %ptr0) { ret i32 0 }
|
||||
define i32 @fun4(i32* %ptr0) { ret i32 0 }
|
||||
...
|
||||
|
||||
|
||||
# Test CGR -> CG
|
||||
# CHECK: name: fun1
|
||||
# CHECK: CG %10, %stack.0, 0, $noreg, implicit-def $cc :: (load 8 from %stack.0)
|
||||
# CHECK-NEXT: %12:gr64bit = LOCGHI %12, 8, 14, 12, implicit killed $cc
|
||||
---
|
||||
name: fun1
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: addr64bit }
|
||||
- { id: 1, class: gr64bit }
|
||||
- { id: 2, class: gr64bit }
|
||||
- { id: 3, class: gr64bit }
|
||||
- { id: 4, class: gr64bit }
|
||||
- { id: 5, class: gr64bit }
|
||||
- { id: 6, class: gr64bit }
|
||||
- { id: 7, class: gr64bit }
|
||||
- { id: 8, class: gr64bit }
|
||||
- { id: 9, class: gr64bit }
|
||||
- { id: 10, class: gr64bit }
|
||||
- { id: 11, class: gr64bit }
|
||||
- { id: 12, class: gr64bit }
|
||||
- { id: 13, class: gr64bit }
|
||||
- { id: 14, class: gr64bit }
|
||||
- { id: 15, class: gr64bit }
|
||||
- { id: 16, class: gr64bit }
|
||||
- { id: 17, class: gr64bit }
|
||||
- { id: 18, class: gr64bit }
|
||||
- { id: 19, class: gr64bit }
|
||||
liveins:
|
||||
- { reg: '$r2d', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
hasCalls: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r2d
|
||||
|
||||
%0:addr64bit = COPY $r2d
|
||||
%1:gr64bit = LG %0, 0, $noreg
|
||||
%2:gr64bit = LG %0, 16, $noreg
|
||||
%3:gr64bit = LG %0, 32, $noreg
|
||||
%4:gr64bit = LG %0, 48, $noreg
|
||||
%5:gr64bit = LG %0, 64, $noreg
|
||||
%6:gr64bit = LG %0, 80, $noreg
|
||||
%7:gr64bit = LG %0, 96, $noreg
|
||||
%8:gr64bit = LG %0, 112, $noreg
|
||||
%9:gr64bit = LG %0, 128, $noreg
|
||||
ADJCALLSTACKDOWN 0, 0
|
||||
CallBRASL @foo, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2d
|
||||
%10:gr64bit = COPY $r2d
|
||||
ADJCALLSTACKUP 0, 0
|
||||
CGR %10, %1, implicit-def $cc
|
||||
%12:gr64bit = COPY %10
|
||||
%12:gr64bit = LOCGHI %12, 0, 14, 10, implicit killed $cc
|
||||
CGR %10, %2, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 1, 14, 10, implicit killed $cc
|
||||
CGR %10, %3, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 2, 14, 10, implicit killed $cc
|
||||
CGR %10, %4, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 3, 14, 10, implicit killed $cc
|
||||
CGR %10, %5, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 4, 14, 10, implicit killed $cc
|
||||
CGR %10, %6, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 5, 14, 10, implicit killed $cc
|
||||
CGR %10, %7, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 6, 14, 10, implicit killed $cc
|
||||
CGR %10, %8, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 7, 14, 10, implicit killed $cc
|
||||
CGR %9, %10, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 8, 14, 10, implicit killed $cc
|
||||
$r2d = COPY %12
|
||||
Return implicit $r2d
|
||||
...
|
||||
|
||||
|
||||
# Test CLGR -> CLG
|
||||
# CHECK: name: fun2
|
||||
# CHECK: CLG %10, %stack.0, 0, $noreg, implicit-def $cc :: (load 8 from %stack.0)
|
||||
# CHECK-NEXT: %12:gr64bit = LOCGHI %12, 8, 14, 12, implicit killed $cc
|
||||
---
|
||||
name: fun2
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: addr64bit }
|
||||
- { id: 1, class: gr64bit }
|
||||
- { id: 2, class: gr64bit }
|
||||
- { id: 3, class: gr64bit }
|
||||
- { id: 4, class: gr64bit }
|
||||
- { id: 5, class: gr64bit }
|
||||
- { id: 6, class: gr64bit }
|
||||
- { id: 7, class: gr64bit }
|
||||
- { id: 8, class: gr64bit }
|
||||
- { id: 9, class: gr64bit }
|
||||
- { id: 10, class: gr64bit }
|
||||
- { id: 11, class: gr64bit }
|
||||
- { id: 12, class: gr64bit }
|
||||
- { id: 13, class: gr64bit }
|
||||
- { id: 14, class: gr64bit }
|
||||
- { id: 15, class: gr64bit }
|
||||
- { id: 16, class: gr64bit }
|
||||
- { id: 17, class: gr64bit }
|
||||
- { id: 18, class: gr64bit }
|
||||
- { id: 19, class: gr64bit }
|
||||
liveins:
|
||||
- { reg: '$r2d', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
hasCalls: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r2d
|
||||
|
||||
%0:addr64bit = COPY $r2d
|
||||
%1:gr64bit = LG %0, 0, $noreg
|
||||
%2:gr64bit = LG %0, 16, $noreg
|
||||
%3:gr64bit = LG %0, 32, $noreg
|
||||
%4:gr64bit = LG %0, 48, $noreg
|
||||
%5:gr64bit = LG %0, 64, $noreg
|
||||
%6:gr64bit = LG %0, 80, $noreg
|
||||
%7:gr64bit = LG %0, 96, $noreg
|
||||
%8:gr64bit = LG %0, 112, $noreg
|
||||
%9:gr64bit = LG %0, 128, $noreg
|
||||
ADJCALLSTACKDOWN 0, 0
|
||||
CallBRASL @foo, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2d
|
||||
%10:gr64bit = COPY $r2d
|
||||
ADJCALLSTACKUP 0, 0
|
||||
CGR %10, %1, implicit-def $cc
|
||||
%12:gr64bit = COPY %10
|
||||
%12:gr64bit = LOCGHI %12, 0, 14, 10, implicit killed $cc
|
||||
CGR %10, %2, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 1, 14, 10, implicit killed $cc
|
||||
CGR %10, %3, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 2, 14, 10, implicit killed $cc
|
||||
CGR %10, %4, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 3, 14, 10, implicit killed $cc
|
||||
CGR %10, %5, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 4, 14, 10, implicit killed $cc
|
||||
CGR %10, %6, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 5, 14, 10, implicit killed $cc
|
||||
CGR %10, %7, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 6, 14, 10, implicit killed $cc
|
||||
CGR %10, %8, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 7, 14, 10, implicit killed $cc
|
||||
CLGR %9, %10, implicit-def $cc
|
||||
%12:gr64bit = LOCGHI %12, 8, 14, 10, implicit killed $cc
|
||||
$r2d = COPY %12
|
||||
Return implicit $r2d
|
||||
...
|
||||
|
||||
|
||||
# Test CR -> C
|
||||
# CHECK: name: fun3
|
||||
# CHECK: C %10, %stack.0, 0, $noreg, implicit-def $cc :: (load 4 from %stack.0)
|
||||
# CHECK: %12:gr32bit = LOCHIMux %12, 8, 14, 12, implicit killed $cc
|
||||
---
|
||||
name: fun3
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: addr64bit }
|
||||
- { id: 1, class: gr32bit }
|
||||
- { id: 2, class: gr32bit }
|
||||
- { id: 3, class: gr32bit }
|
||||
- { id: 4, class: gr32bit }
|
||||
- { id: 5, class: gr32bit }
|
||||
- { id: 6, class: gr32bit }
|
||||
- { id: 7, class: gr32bit }
|
||||
- { id: 8, class: gr32bit }
|
||||
- { id: 9, class: gr32bit }
|
||||
- { id: 10, class: gr32bit }
|
||||
- { id: 11, class: gr32bit }
|
||||
- { id: 12, class: gr32bit }
|
||||
- { id: 13, class: gr32bit }
|
||||
- { id: 14, class: gr32bit }
|
||||
- { id: 15, class: gr32bit }
|
||||
- { id: 16, class: gr32bit }
|
||||
- { id: 17, class: gr32bit }
|
||||
- { id: 18, class: gr32bit }
|
||||
- { id: 19, class: gr32bit }
|
||||
liveins:
|
||||
- { reg: '$r2d', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
hasCalls: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r2d
|
||||
|
||||
%0:addr64bit = COPY $r2d
|
||||
%1:gr32bit = LMux %0, 0, $noreg
|
||||
%2:gr32bit = LMux %0, 8, $noreg
|
||||
%3:gr32bit = LMux %0, 16, $noreg
|
||||
%4:gr32bit = LMux %0, 24, $noreg
|
||||
%5:gr32bit = LMux %0, 32, $noreg
|
||||
%6:gr32bit = LMux %0, 40, $noreg
|
||||
%7:gr32bit = LMux %0, 48, $noreg
|
||||
%8:gr32bit = LMux %0, 56, $noreg
|
||||
%9:gr32bit = LMux %0, 64, $noreg
|
||||
ADJCALLSTACKDOWN 0, 0
|
||||
CallBRASL @foo, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2l
|
||||
%10:gr32bit = COPY $r2l
|
||||
ADJCALLSTACKUP 0, 0
|
||||
CR %10, %1, implicit-def $cc
|
||||
%12:gr32bit = COPY %10
|
||||
%12:gr32bit = LOCHIMux %12, 0, 14, 10, implicit killed $cc
|
||||
CR %10, %2, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 1, 14, 10, implicit killed $cc
|
||||
CR %10, %3, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 2, 14, 10, implicit killed $cc
|
||||
CR %10, %4, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 3, 14, 10, implicit killed $cc
|
||||
CR %10, %5, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 4, 14, 10, implicit killed $cc
|
||||
CR %10, %6, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 5, 14, 10, implicit killed $cc
|
||||
CR %10, %7, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 6, 14, 10, implicit killed $cc
|
||||
CR %10, %8, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 7, 14, 10, implicit killed $cc
|
||||
CR %9, %10, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 8, 14, 10, implicit killed $cc
|
||||
$r2l = COPY %12
|
||||
Return implicit $r2l
|
||||
...
|
||||
|
||||
|
||||
# Test CLR -> CL
|
||||
# CHECK: name: fun4
|
||||
# CHECK: CL %10, %stack.0, 0, $noreg, implicit-def $cc :: (load 4 from %stack.0)
|
||||
# CHECK: %12:gr32bit = LOCHIMux %12, 8, 14, 12, implicit killed $cc
|
||||
---
|
||||
name: fun4
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: addr64bit }
|
||||
- { id: 1, class: gr32bit }
|
||||
- { id: 2, class: gr32bit }
|
||||
- { id: 3, class: gr32bit }
|
||||
- { id: 4, class: gr32bit }
|
||||
- { id: 5, class: gr32bit }
|
||||
- { id: 6, class: gr32bit }
|
||||
- { id: 7, class: gr32bit }
|
||||
- { id: 8, class: gr32bit }
|
||||
- { id: 9, class: gr32bit }
|
||||
- { id: 10, class: gr32bit }
|
||||
- { id: 11, class: gr32bit }
|
||||
- { id: 12, class: gr32bit }
|
||||
- { id: 13, class: gr32bit }
|
||||
- { id: 14, class: gr32bit }
|
||||
- { id: 15, class: gr32bit }
|
||||
- { id: 16, class: gr32bit }
|
||||
- { id: 17, class: gr32bit }
|
||||
- { id: 18, class: gr32bit }
|
||||
- { id: 19, class: gr32bit }
|
||||
liveins:
|
||||
- { reg: '$r2d', virtual-reg: '%0' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
hasCalls: true
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $r2d
|
||||
|
||||
%0:addr64bit = COPY $r2d
|
||||
%1:gr32bit = LMux %0, 0, $noreg
|
||||
%2:gr32bit = LMux %0, 8, $noreg
|
||||
%3:gr32bit = LMux %0, 16, $noreg
|
||||
%4:gr32bit = LMux %0, 24, $noreg
|
||||
%5:gr32bit = LMux %0, 32, $noreg
|
||||
%6:gr32bit = LMux %0, 40, $noreg
|
||||
%7:gr32bit = LMux %0, 48, $noreg
|
||||
%8:gr32bit = LMux %0, 56, $noreg
|
||||
%9:gr32bit = LMux %0, 64, $noreg
|
||||
ADJCALLSTACKDOWN 0, 0
|
||||
CallBRASL @foo, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2l
|
||||
%10:gr32bit = COPY $r2l
|
||||
ADJCALLSTACKUP 0, 0
|
||||
CR %10, %1, implicit-def $cc
|
||||
%12:gr32bit = COPY %10
|
||||
%12:gr32bit = LOCHIMux %12, 0, 14, 10, implicit killed $cc
|
||||
CR %10, %2, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 1, 14, 10, implicit killed $cc
|
||||
CR %10, %3, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 2, 14, 10, implicit killed $cc
|
||||
CR %10, %4, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 3, 14, 10, implicit killed $cc
|
||||
CR %10, %5, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 4, 14, 10, implicit killed $cc
|
||||
CR %10, %6, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 5, 14, 10, implicit killed $cc
|
||||
CR %10, %7, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 6, 14, 10, implicit killed $cc
|
||||
CR %10, %8, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 7, 14, 10, implicit killed $cc
|
||||
CLR %9, %10, implicit-def $cc
|
||||
%12:gr32bit = LOCHIMux %12, 8, 14, 10, implicit killed $cc
|
||||
$r2l = COPY %12
|
||||
Return implicit $r2l
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user