diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index a07b7be00d2..875c758b1ad 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -1104,10 +1104,12 @@ void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, assert(Val == MO.getImm() && "Add/sub immediate out of range!"); unsigned Shift = ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); - O << '#' << (Val << Shift); - // Distinguish "0, lsl #12" from "0, lsl #0". - if (Val == 0 && Shift != 0) + O << '#' << Val; + if (Shift != 0) printShifter(MI, OpNum + 1, O); + + if (CommentStream) + *CommentStream << "=#" << (Val << Shift) << '\n'; } else { assert(MO.isExpr() && "Unexpected operand type!"); O << *MO.getExpr(); diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index 5d7b6250d79..f73365b20c2 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -136,7 +136,7 @@ define void @test_alloca_large_frame(i64 %n) { ; CHECK-ARM64: stp x20, x19, [sp, #-32]! ; CHECK-ARM64: stp x29, x30, [sp, #16] ; CHECK-ARM64: add x29, sp, #16 -; CHECK-ARM64: sub sp, sp, #7999488 +; CHECK-ARM64: sub sp, sp, #1953, lsl #12 ; CHECK-ARM64: sub sp, sp, #512 %addr1 = alloca i8, i64 %n diff --git a/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll b/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll index ea1cd02ca22..8f99bc30a55 100644 --- a/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll +++ b/test/CodeGen/ARM64/2011-10-18-LdStOptBug.ll @@ -14,7 +14,7 @@ for.body: ; CHECK: for.body ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}] ; CHECK: add x[[REG:[0-9]+]], -; CHECK: x[[REG]], #4096 +; CHECK: x[[REG]], #1, lsl #12 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %0 = shl nsw i64 %indvars.iv, 12 %add = add nsw i64 %0, 34628173824 diff --git a/test/CodeGen/ARM64/aarch64-large-frame.ll b/test/CodeGen/ARM64/aarch64-large-frame.ll index 011affa178c..5a53da69388 100644 --- a/test/CodeGen/ARM64/aarch64-large-frame.ll +++ b/test/CodeGen/ARM64/aarch64-large-frame.ll @@ -11,23 +11,23 @@ define void @test_bigframe() { %var2 = alloca i8, i32 16 %var3 = alloca i8, i32 20000000 -; CHECK: sub sp, sp, #16773120 -; CHECK: sub sp, sp, #16773120 -; CHECK: sub sp, sp, #6451200 +; CHECK: sub sp, sp, #4095, lsl #12 +; CHECK: sub sp, sp, #4095, lsl #12 +; CHECK: sub sp, sp, #1575, lsl #12 ; CHECK: sub sp, sp, #2576 ; CHECK: .cfi_def_cfa_offset 40000032 -; CHECK: add [[TMP:x[0-9]+]], sp, #16773120 -; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #3223552 +; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12 +; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344 store volatile i8* %var1, i8** @addr %var1plus2 = getelementptr i8* %var1, i32 2 store volatile i8* %var1plus2, i8** @addr -; CHECK: add [[TMP:x[0-9]+]], sp, #16773120 -; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #3223552 +; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12 +; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12 ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328 store volatile i8* %var2, i8** @addr @@ -39,9 +39,9 @@ define void @test_bigframe() { %var3plus2 = getelementptr i8* %var3, i32 2 store volatile i8* %var3plus2, i8** @addr -; CHECK: add sp, sp, #16773120 -; CHECK: add sp, sp, #16773120 -; CHECK: add sp, sp, #6451200 +; CHECK: add sp, sp, #4095, lsl #12 +; CHECK: add sp, sp, #4095, lsl #12 +; CHECK: add sp, sp, #1575, lsl #12 ; CHECK: add sp, sp, #2576 ; CHECK: .cfi_endproc ret void @@ -52,18 +52,18 @@ define void @test_mediumframe() { %var1 = alloca i8, i32 1000000 %var2 = alloca i8, i32 16 %var3 = alloca i8, i32 1000000 -; CHECK: sub sp, sp, #1998848 +; CHECK: sub sp, sp, #488, lsl #12 ; CHECK-NEXT: sub sp, sp, #1168 store volatile i8* %var1, i8** @addr -; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #999424 +; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12 ; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #592 -; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #999424 +; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12 ; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576 store volatile i8* %var2, i8** @addr -; CHECK: add sp, sp, #1998848 +; CHECK: add sp, sp, #488, lsl #12 ; CHECK: add sp, sp, #1168 ret void } diff --git a/test/CodeGen/ARM64/addrmode.ll b/test/CodeGen/ARM64/addrmode.ll index e1312376e2b..700fba80149 100644 --- a/test/CodeGen/ARM64/addrmode.ll +++ b/test/CodeGen/ARM64/addrmode.ll @@ -37,7 +37,7 @@ define void @t3() { ; base + unsigned offset (> imm12 * size of type in bytes) ; CHECK: @t4 -; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #32768 +; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, #8, lsl #12 ; CHECK: ldr xzr, [ ; CHECK: [[ADDREG]]] ; CHECK: ret @@ -60,7 +60,7 @@ define void @t5(i64 %a) { ; base + reg + imm ; CHECK: @t6 ; CHECK: add [[ADDREG:x[0-9]+]], x{{[0-9]+}}, x{{[0-9]+}}, lsl #3 -; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #32768 +; CHECK-NEXT: add [[ADDREG]], [[ADDREG]], #8, lsl #12 ; CHECK: ldr xzr, [ ; CHECK: [[ADDREG]]] ; CHECK: ret diff --git a/test/CodeGen/ARM64/atomic.ll b/test/CodeGen/ARM64/atomic.ll index dbdc95c428f..b446f3e499b 100644 --- a/test/CodeGen/ARM64/atomic.ll +++ b/test/CodeGen/ARM64/atomic.ll @@ -128,7 +128,7 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) { %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) %val_random = load atomic i8* %ptr_random unordered, align 1 %tot3 = add i8 %tot2, %val_random -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]] ret i8 %tot3 @@ -153,7 +153,7 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) { %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) %val_random = load atomic i16* %ptr_random unordered, align 2 %tot3 = add i16 %tot2, %val_random -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]] ret i16 %tot3 @@ -178,7 +178,7 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) { %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) %val_random = load atomic i32* %ptr_random unordered, align 4 %tot3 = add i32 %tot2, %val_random -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]] ret i32 %tot3 @@ -203,7 +203,7 @@ define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) { %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) %val_random = load atomic i64* %ptr_random unordered, align 8 %tot3 = add i64 %tot2, %val_random -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]] ret i64 %tot3 @@ -233,7 +233,7 @@ define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) { %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) store atomic i8 %val, i8* %ptr_random unordered, align 1 -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]] ret void @@ -255,7 +255,7 @@ define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) { %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) store atomic i16 %val, i16* %ptr_random unordered, align 2 -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]] ret void @@ -277,7 +277,7 @@ define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) { %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) store atomic i32 %val, i32* %ptr_random unordered, align 4 -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]] ret void @@ -299,7 +299,7 @@ define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) { %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) store atomic i64 %val, i64* %ptr_random unordered, align 8 -; CHECK: add x[[ADDR:[0-9]+]], x0, #1191936 +; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]] ret void diff --git a/test/CodeGen/ARM64/big-stack.ll b/test/CodeGen/ARM64/big-stack.ll index 56ca30c17b4..3f91bb3c248 100644 --- a/test/CodeGen/ARM64/big-stack.ll +++ b/test/CodeGen/ARM64/big-stack.ll @@ -7,9 +7,9 @@ target triple = "arm64-apple-macosx10" ; shift left (up to 12). I.e., 16773120 is the biggest value. ; ; CHECK-LABEL: foo: -; CHECK: sub sp, sp, #16773120 -; CHECK: sub sp, sp, #16773120 -; CHECK: sub sp, sp, #8192 +; CHECK: sub sp, sp, #4095, lsl #12 +; CHECK: sub sp, sp, #4095, lsl #12 +; CHECK: sub sp, sp, #2, lsl #12 define void @foo() nounwind ssp { entry: %buffer = alloca [33554432 x i8], align 1 diff --git a/test/CodeGen/ARM64/dead-def-frame-index.ll b/test/CodeGen/ARM64/dead-def-frame-index.ll index 4f8cc859ee9..9bb4b712076 100644 --- a/test/CodeGen/ARM64/dead-def-frame-index.ll +++ b/test/CodeGen/ARM64/dead-def-frame-index.ll @@ -13,6 +13,6 @@ define i32 @test1() #0 { ret i32 %tmp4 ; CHECK-LABEL: test1 - ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #16384 + ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12 ; CHECK: adds [[TEMP]], [[TEMP]], #15 } diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s index a1d1e8349b7..df746b3c8aa 100644 --- a/test/MC/ARM64/aliases.s +++ b/test/MC/ARM64/aliases.s @@ -67,7 +67,7 @@ foo: cmn x4, x5, uxtx #1 ; CHECK: cmn w1, #3 ; encoding: [0x3f,0x0c,0x00,0x31] -; CHECK: cmn x2, #4194304 ; encoding: [0x5f,0x00,0x50,0xb1] +; CHECK: cmn x2, #1024, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1] ; CHECK: cmn w4, w5 ; encoding: [0x9f,0x00,0x05,0x2b] ; CHECK: cmn x6, x7 ; encoding: [0xdf,0x00,0x07,0xab] ; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b] @@ -92,7 +92,7 @@ foo: cmp w9, w8, uxtw cmp wsp, w9, lsl #0 -; CHECK: cmp w1, #4194304 ; encoding: [0x3f,0x00,0x50,0x71] +; CHECK: cmp w1, #1024, lsl #12 ; encoding: [0x3f,0x00,0x50,0x71] ; CHECK: cmp x2, #1024 ; encoding: [0x5f,0x00,0x10,0xf1] ; CHECK: cmp w4, w5 ; encoding: [0x9f,0x00,0x05,0x6b] ; CHECK: cmp x6, x7 ; encoding: [0xdf,0x00,0x07,0xeb] diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s index 2193feb3f6a..6dd8ba1521a 100644 --- a/test/MC/ARM64/arithmetic-encoding.s +++ b/test/MC/ARM64/arithmetic-encoding.s @@ -47,11 +47,11 @@ foo: add x3, x4, #0, lsl #12 add sp, sp, #32 -; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11] -; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] ; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11] -; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91] -; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] ; CHECK: add x3, x4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x91] ; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91] @@ -64,10 +64,10 @@ foo: ; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] ; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] -; CHECK: adds w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x31] +; CHECK: adds w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x31] ; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] ; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] -; CHECK: adds x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xb1] +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] sub w3, w4, #1024 sub w3, w4, #1024, lsl #0 @@ -79,10 +79,10 @@ foo: ; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] ; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] -; CHECK: sub w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x51] +; CHECK: sub w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x51] ; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] ; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] -; CHECK: sub x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xd1] +; CHECK: sub x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xd1] ; CHECK: sub sp, sp, #32 ; encoding: [0xff,0x83,0x00,0xd1] subs w3, w4, #1024 @@ -94,10 +94,10 @@ foo: ; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] ; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] -; CHECK: subs w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x71] +; CHECK: subs w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x71] ; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] ; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] -; CHECK: subs x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xf1] +; CHECK: subs x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xf1] ;==---------------------------------------------------------------------------== ; Add/Subtract register with (optional) shift diff --git a/test/MC/ARM64/optional-hash.s b/test/MC/ARM64/optional-hash.s index c67c124c31a..f7c5e21832e 100644 --- a/test/MC/ARM64/optional-hash.s +++ b/test/MC/ARM64/optional-hash.s @@ -5,7 +5,7 @@ add sp, sp, 32 ; Optional shift -; CHECK: adds x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xb1] +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] adds x3, x4, 1024, lsl 12 ; Optional extend diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/ARM64/arithmetic.txt index d68f43bd331..5e98fca9592 100644 --- a/test/MC/Disassembler/ARM64/arithmetic.txt +++ b/test/MC/Disassembler/ARM64/arithmetic.txt @@ -40,8 +40,8 @@ 0x83 0x00 0x40 0x91 0xff 0x83 0x00 0x91 -# CHECK: add w3, w4, #4194304 -# CHECK: add x3, x4, #4194304 +# CHECK: add w3, w4, #1024, lsl #12 +# CHECK: add x3, x4, #1024, lsl #12 # CHECK: add x3, x4, #0, lsl #12 # CHECK: add sp, sp, #32 @@ -52,9 +52,9 @@ 0xff 0x83 0x00 0xb1 # CHECK: adds w3, w4, #1024 -# CHECK: adds w3, w4, #4194304 +# CHECK: adds w3, w4, #1024, lsl #12 # CHECK: adds x3, x4, #1024 -# CHECK: adds x3, x4, #4194304 +# CHECK: adds x3, x4, #1024, lsl #12 # CHECK: cmn sp, #32 0x83 0x00 0x10 0x51 @@ -64,9 +64,9 @@ 0xff 0x83 0x00 0xd1 # CHECK: sub w3, w4, #1024 -# CHECK: sub w3, w4, #4194304 +# CHECK: sub w3, w4, #1024, lsl #12 # CHECK: sub x3, x4, #1024 -# CHECK: sub x3, x4, #4194304 +# CHECK: sub x3, x4, #1024, lsl #12 # CHECK: sub sp, sp, #32 0x83 0x00 0x10 0x71 @@ -76,9 +76,9 @@ 0xff 0x83 0x00 0xf1 # CHECK: subs w3, w4, #1024 -# CHECK: subs w3, w4, #4194304 +# CHECK: subs w3, w4, #1024, lsl #12 # CHECK: subs x3, x4, #1024 -# CHECK: subs x3, x4, #4194304 +# CHECK: subs x3, x4, #1024, lsl #12 # CHECK: cmp sp, #32 #==---------------------------------------------------------------------------==