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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 03:02:36 +01:00
Make it possible for the Subtarget to change between function
passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. llvm-svn: 212744
This commit is contained in:
Eric Christopher
parent
44ec851704
commit
3599325ed0
@ -37,7 +37,7 @@ using namespace llvm;
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#define DEBUG_TYPE "mips-isel"
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bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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if (!Subtarget.inMips16Mode())
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if (!Subtarget->inMips16Mode())
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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@ -226,9 +226,9 @@ bool Mips16DAGToDAGISel::selectAddr16(
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const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
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if (LS) {
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if (LS->getMemoryVT() == MVT::f32 && Subtarget.hasMips4_32r2())
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if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
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return false;
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if (LS->getMemoryVT() == MVT::f64 && Subtarget.hasMips4_32r2())
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if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
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return false;
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}
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}
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@ -7,9 +7,9 @@
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//
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//===----------------------------------------------------------------------===//
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def HasDSP : Predicate<"Subtarget.hasDSP()">,
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def HasDSP : Predicate<"Subtarget->hasDSP()">,
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AssemblerPredicate<"FeatureDSP">;
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def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
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def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
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AssemblerPredicate<"FeatureDSPR2">;
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// Fields.
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@ -41,7 +41,7 @@ class MipsFastISel final : public FastISel {
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const MipsSubtarget &Subtarget;
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const MipsSubtarget *Subtarget;
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MipsFunctionInfo *MFI;
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// Convenience variables to avoid some queries.
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@ -56,11 +56,11 @@ public:
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M(const_cast<Module &>(*funcInfo.Fn->getParent())),
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TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()),
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Subtarget(TM.getSubtarget<MipsSubtarget>()) {
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Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
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MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
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Context = &funcInfo.Fn->getContext();
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TargetSupported = ((Subtarget.getRelocationModel() == Reloc::PIC_) &&
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(Subtarget.hasMips32r2() && (Subtarget.isABI_O32())));
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TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
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(Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
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}
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bool TargetSelectInstruction(const Instruction *I) override;
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@ -47,6 +47,7 @@ using namespace llvm;
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//===----------------------------------------------------------------------===//
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bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
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processFunctionAfterISel(MF);
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@ -202,7 +203,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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#ifndef NDEBUG
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case ISD::LOAD:
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case ISD::STORE:
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assert((Subtarget.systemSupportsUnalignedAccess() ||
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assert((Subtarget->systemSupportsUnalignedAccess() ||
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cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
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cast<MemSDNode>(Node)->getAlignment()) &&
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"Unexpected unaligned loads/stores.");
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@ -32,7 +32,7 @@ namespace llvm {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
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: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
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: SelectionDAGISel(TM), Subtarget(&TM.getSubtarget<MipsSubtarget>()) {}
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// Pass Name
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const char *getPassName() const override {
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@ -46,7 +46,7 @@ protected:
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/// Keep a pointer to the MipsSubtarget around so that we can make the right
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/// decision when generating code for different targets.
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const MipsSubtarget &Subtarget;
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const MipsSubtarget *Subtarget;
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private:
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// Include the pieces autogenerated from the target description.
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@ -57,13 +57,13 @@ let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
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def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
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AssemblerPredicate<"FeatureFP64Bit">;
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def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
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def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
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AssemblerPredicate<"!FeatureFP64Bit">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
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def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">,
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AssemblerPredicate<"FeatureSingleFloat">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
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def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
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AssemblerPredicate<"!FeatureSingleFloat">;
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//===----------------------------------------------------------------------===//
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@ -146,61 +146,61 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasMips2 : Predicate<"Subtarget.hasMips2()">,
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def HasMips2 : Predicate<"Subtarget->hasMips2()">,
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AssemblerPredicate<"FeatureMips2">;
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def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
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def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
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AssemblerPredicate<"FeatureMips3_32">;
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def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
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def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
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AssemblerPredicate<"FeatureMips3_32r2">;
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def HasMips3 : Predicate<"Subtarget.hasMips3()">,
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def HasMips3 : Predicate<"Subtarget->hasMips3()">,
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AssemblerPredicate<"FeatureMips3">;
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def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
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def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
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AssemblerPredicate<"FeatureMips4_32">;
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def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
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def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
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AssemblerPredicate<"FeatureMips4_32r2">;
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def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
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def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
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AssemblerPredicate<"FeatureMips5_32r2">;
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def HasMips32 : Predicate<"Subtarget.hasMips32()">,
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def HasMips32 : Predicate<"Subtarget->hasMips32()">,
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AssemblerPredicate<"FeatureMips32">;
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def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
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def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
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AssemblerPredicate<"FeatureMips32r2">;
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def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
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def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
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AssemblerPredicate<"FeatureMips32r6">;
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def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
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def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
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AssemblerPredicate<"!FeatureMips32r6">;
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def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
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def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
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AssemblerPredicate<"FeatureGP64Bit">;
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def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
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def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
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AssemblerPredicate<"!FeatureGP64Bit">;
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def HasMips64 : Predicate<"Subtarget.hasMips64()">,
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def HasMips64 : Predicate<"Subtarget->hasMips64()">,
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AssemblerPredicate<"FeatureMips64">;
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def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
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def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
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AssemblerPredicate<"FeatureMips64r2">;
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def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
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def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
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AssemblerPredicate<"FeatureMips64r6">;
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def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
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def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
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AssemblerPredicate<"!FeatureMips64r6">;
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def IsN64 : Predicate<"Subtarget.isABI_N64()">,
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def IsN64 : Predicate<"Subtarget->isABI_N64()">,
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AssemblerPredicate<"FeatureN64">;
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def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
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def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
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def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
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def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
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AssemblerPredicate<"FeatureCnMips">;
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def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
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AssemblerPredicate<"FeatureMips32">;
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def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
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AssemblerPredicate<"FeatureMips32">;
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def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
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def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
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def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
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AssemblerPredicate<"!FeatureMips16">;
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def NotDSP : Predicate<"!Subtarget.hasDSP()">;
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def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
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def NotDSP : Predicate<"!Subtarget->hasDSP()">;
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def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
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AssemblerPredicate<"FeatureMicroMips">;
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def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
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def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
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AssemblerPredicate<"!FeatureMicroMips">;
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def IsLE : Predicate<"Subtarget.isLittle()">;
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def IsBE : Predicate<"!Subtarget.isLittle()">;
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def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
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def IsLE : Predicate<"Subtarget->isLittle()">;
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def IsBE : Predicate<"!Subtarget->isLittle()">;
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def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
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//===----------------------------------------------------------------------===//
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// Mips GPR size adjectives.
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@ -7,7 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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def HasMSA : Predicate<"Subtarget.hasMSA()">,
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def HasMSA : Predicate<"Subtarget->hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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@ -37,7 +37,7 @@ using namespace llvm;
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#define DEBUG_TYPE "mips-isel"
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bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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if (Subtarget.inMips16Mode())
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if (Subtarget->inMips16Mode())
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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@ -134,7 +134,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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const TargetRegisterClass *RC;
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if (Subtarget.isABI_N64())
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if (Subtarget->isABI_N64())
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RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
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else
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RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
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@ -142,7 +142,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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if (Subtarget.isABI_N64()) {
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if (Subtarget->isABI_N64()) {
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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MBB.addLiveIn(Mips::T9_64);
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@ -174,7 +174,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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if (Subtarget.isABI_N32()) {
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if (Subtarget->isABI_N32()) {
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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@ -187,7 +187,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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return;
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}
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assert(Subtarget.isABI_O32());
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assert(Subtarget->isABI_O32());
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// For O32 ABI, the following instruction sequence is emitted to initialize
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// the global base register:
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@ -408,7 +408,7 @@ bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
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// * MSA is enabled
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// * N is a ISD::BUILD_VECTOR representing a constant splat
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bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
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if (!Subtarget.hasMSA())
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if (!Subtarget->hasMSA())
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return false;
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BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
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@ -422,7 +422,7 @@ bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
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if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
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HasAnyUndefs, 8,
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!Subtarget.isLittle()))
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!Subtarget->isLittle()))
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return false;
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Imm = SplatValue;
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@ -648,7 +648,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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}
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case ISD::ADDE: {
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if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
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if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
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break;
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SDValue InFlag = Node->getOperand(2);
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Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
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@ -658,11 +658,11 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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if (Subtarget.isGP64bit()) {
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if (Subtarget->isGP64bit()) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
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Mips::ZERO_64, MVT::i64);
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Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
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} else if (Subtarget.isFP64bit()) {
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} else if (Subtarget->isFP64bit()) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
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Mips::ZERO, MVT::i32);
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Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
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@ -813,12 +813,12 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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EVT ResVecTy = BVN->getValueType(0);
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EVT ViaVecTy;
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if (!Subtarget.hasMSA() || !BVN->getValueType(0).is128BitVector())
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if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
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return std::make_pair(false, nullptr);
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if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
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HasAnyUndefs, 8,
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!Subtarget.isLittle()))
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!Subtarget->isLittle()))
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return std::make_pair(false, nullptr);
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switch (SplatBitSize) {
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