diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index b7a9f6f3179..9ec03bf8f70 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -9158,7 +9158,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
         // Blacklist CopyFromReg to avoid partial register stalls.
         T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
       SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
-      SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T1, T2, CC, Cond);
+      SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
       return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
     }
   }
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
index f4c8d9e767c..3bec3acdbf7 100644
--- a/test/CodeGen/X86/select.ll
+++ b/test/CodeGen/X86/select.ll
@@ -350,10 +350,10 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
   %sel = select i1 %cmp, i8 %a, i8 %b
   ret i8 %sel
 ; CHECK: test18:
-; CHECK: cmpl $15
-; CHECK: cmovll
+; CHECK: cmpl $15, %edi
+; CHECK: cmovgel %edx
 
 ; ATOM: test18:
-; ATOM: cmpl $15
-; ATOM: cmovll
+; ATOM: cmpl $15, %edi
+; ATOM: cmovgel %edx
 }