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[AArch64][SVE] Asm: Support for gather PRF prefetch instructions
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46686 llvm-svn: 332472
This commit is contained in:
Sander de Smalen
parent
5b328a4e1c
commit
3667e06eb4
@ -386,6 +386,40 @@ let Predicates = [HasSVE] in {
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def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>;
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def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>;
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// Gather prefetch using scaled 32-bit offsets, e.g.
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// prfh pldl1keep, p0, [x0, z0.s, uxtw #1]
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defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>;
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// Gather prefetch using unpacked, scaled 32-bit offsets, e.g.
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// prfh pldl1keep, p0, [x0, z0.d, uxtw #1]
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defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Gather prefetch using scaled 64-bit offsets, e.g.
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// prfh pldl1keep, p0, [x0, z0.d, lsl #1]
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defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>;
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defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>;
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defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>;
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defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>;
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// Gather prefetch using 32/64-bit pointers with offset, e.g.
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// prfh pldl1keep, p0, [z0.s, #16]
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// prfh pldl1keep, p0, [z0.d, #16]
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defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>;
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defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>;
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defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>;
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defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>;
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defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>;
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defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>;
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defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>;
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defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>;
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defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
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defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
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@ -1325,6 +1325,64 @@ class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
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let hasSideEffects = 1;
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}
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class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
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RegisterOperand zprext>
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: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
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asm, "\t$prfop, $Pg, [$Rn, $Zm]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rn;
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bits<5> Zm;
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bits<4> prfop;
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let Inst{31-23} = 0b100001000;
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let Inst{22} = xs;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15} = 0b0;
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let Inst{14-13} = msz;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4} = 0b0;
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let Inst{3-0} = prfop;
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let hasSideEffects = 1;
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}
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multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
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RegisterOperand sxtw_opnd,
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RegisterOperand uxtw_opnd> {
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def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
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def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
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}
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class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
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: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
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asm, "\t$prfop, $Pg, [$Zn, $imm5]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Zn;
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bits<5> imm5;
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bits<4> prfop;
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let Inst{31-25} = 0b1000010;
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let Inst{24-23} = msz;
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let Inst{22-21} = 0b00;
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let Inst{20-16} = imm5;
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let Inst{15-13} = 0b111;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4} = 0b0;
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let Inst{3-0} = prfop;
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}
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multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
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def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
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def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
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(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
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}
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class sve_mem_z_fill<string asm>
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: I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9),
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asm, "\t$Zt, [$Rn, $imm9, mul vl]",
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@ -1482,3 +1540,70 @@ multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
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def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
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(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
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}
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// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
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class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
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RegisterOperand zprext>
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: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
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asm, "\t$prfop, $Pg, [$Rn, $Zm]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rn;
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bits<5> Zm;
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bits<4> prfop;
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let Inst{31-23} = 0b110001000;
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let Inst{22} = xs;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15} = lsl;
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let Inst{14-13} = msz;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4} = 0b0;
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let Inst{3-0} = prfop;
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let hasSideEffects = 1;
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}
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multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
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RegisterOperand sxtw_opnd,
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RegisterOperand uxtw_opnd> {
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def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
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def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
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}
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multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
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RegisterOperand zprext> {
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def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
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}
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class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
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: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
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asm, "\t$prfop, $Pg, [$Zn, $imm5]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Zn;
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bits<5> imm5;
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bits<4> prfop;
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let Inst{31-25} = 0b1100010;
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let Inst{24-23} = msz;
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let Inst{22-21} = 0b00;
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let Inst{20-16} = imm5;
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let Inst{15-13} = 0b111;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4} = 0b0;
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let Inst{3-0} = prfop;
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let hasSideEffects = 1;
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}
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multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
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def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
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def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
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(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
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}
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@ -26,7 +26,7 @@ prfb #pldl1keep, p0, [x0]
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// --------------------------------------------------------------------------//
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// invalid addressing modes
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// invalid scalar + scalar addressing modes
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prfb #0, p0, [x0, #-33, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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@ -54,6 +54,73 @@ prfb #0, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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prfb #0, p0, [x0, z0.b]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.b]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s, uxtw #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.s, lsl #0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.d, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.d, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [x0, z0.d, sxtw #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
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// CHECK-NEXT: prfb #0, p0, [x0, z0.d, sxtw #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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prfb #0, p0, [z0.s, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.s, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.s, #32]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.s, #32]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfb #0, p0, [z0.d, #32]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
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// CHECK-NEXT: prfb #0, p0, [z0.d, #32]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// invalid predicate
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@ -192,3 +192,57 @@ prfb #1, p0, [x0, #31, mul vl]
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// CHECK-ENCODING: [0x01,0x00,0xdf,0x85]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 01 00 df 85 <unknown>
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prfb pldl1keep, p0, [x0, z0.s, uxtw]
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// CHECK-INST: prfb pldl1keep, p0, [x0, z0.s, uxtw]
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// CHECK-ENCODING: [0x00,0x00,0x20,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 00 20 84 <unknown>
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prfb pldl3strm, p5, [x10, z21.s, uxtw]
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// CHECK-INST: prfb pldl3strm, p5, [x10, z21.s, uxtw]
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// CHECK-ENCODING: [0x45,0x15,0x35,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 45 15 35 84 <unknown>
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prfb pldl1keep, p0, [x0, z0.d, uxtw]
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// CHECK-INST: prfb pldl1keep, p0, [x0, z0.d, uxtw]
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// CHECK-ENCODING: [0x00,0x00,0x20,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 00 20 c4 <unknown>
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prfb pldl3strm, p5, [x10, z21.d, sxtw]
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// CHECK-INST: prfb pldl3strm, p5, [x10, z21.d, sxtw]
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// CHECK-ENCODING: [0x45,0x15,0x75,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 45 15 75 c4 <unknown>
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prfb pldl1keep, p0, [x0, z0.d]
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// CHECK-INST: prfb pldl1keep, p0, [x0, z0.d]
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// CHECK-ENCODING: [0x00,0x80,0x60,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 60 c4 <unknown>
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prfb #7, p3, [z13.s, #0]
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// CHECK-INST: prfb #7, p3, [z13.s]
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// CHECK-ENCODING: [0xa7,0xed,0x00,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a7 ed 00 84 <unknown>
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prfb #7, p3, [z13.s, #31]
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// CHECK-INST: prfb #7, p3, [z13.s, #31]
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// CHECK-ENCODING: [0xa7,0xed,0x1f,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a7 ed 1f 84 <unknown>
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prfb pldl3strm, p5, [z10.d, #0]
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// CHECK-INST: prfb pldl3strm, p5, [z10.d]
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// CHECK-ENCODING: [0x45,0xf5,0x00,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 45 f5 00 c4 <unknown>
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|
||||
prfb pldl3strm, p5, [z10.d, #31]
|
||||
// CHECK-INST: prfb pldl3strm, p5, [z10.d, #31]
|
||||
// CHECK-ENCODING: [0x45,0xf5,0x1f,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 f5 1f c4 <unknown>
|
||||
|
||||
@ -26,7 +26,7 @@ prfd #pldl1keep, p0, [x0]
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid addressing modes
|
||||
// invalid scalar + scalar addressing modes
|
||||
|
||||
prfd #0, p0, [x0, #-33, mul vl]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
|
||||
@ -54,6 +54,59 @@ prfd #0, p0, [x0, x0, lsl #1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + vector addressing modes
|
||||
|
||||
prfd #0, p0, [x0, z0.s]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
|
||||
// CHECK-NEXT: prfd #0, p0, [x0, z0.s]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [x0, z0.d, uxtw #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
|
||||
// CHECK-NEXT: prfd #0, p0, [x0, z0.d, uxtw #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [x0, z0.d, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
|
||||
// CHECK-NEXT: prfd #0, p0, [x0, z0.d, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [x0, z0.d, lsl]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
|
||||
// CHECK-NEXT: prfd #0, p0, [x0, z0.d, lsl]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector + immediate addressing modes
|
||||
|
||||
prfd #0, p0, [z0.d, #-8]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
|
||||
// CHECK-NEXT: prfd #0, p0, [z0.d, #-8]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [z0.d, #-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
|
||||
// CHECK-NEXT: prfd #0, p0, [z0.d, #-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [z0.d, #249]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
|
||||
// CHECK-NEXT: prfd #0, p0, [z0.d, #249]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [z0.d, #256]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
|
||||
// CHECK-NEXT: prfd #0, p0, [z0.d, #256]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfd #0, p0, [z0.d, #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
|
||||
// CHECK-NEXT: prfd #0, p0, [z0.d, #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
|
||||
@ -192,3 +192,57 @@ prfd pldl1strm, p0, [x0, #31, mul vl]
|
||||
// CHECK-ENCODING: [0x01,0x60,0xdf,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 01 60 df 85
|
||||
|
||||
prfd pldl1keep, p0, [x0, z0.s, uxtw #3]
|
||||
// CHECK-INST: prfd pldl1keep, p0, [x0, z0.s, uxtw #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x20,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 20 84 <unknown>
|
||||
|
||||
prfd pldl1keep, p0, [x0, z0.s, sxtw #3]
|
||||
// CHECK-INST: prfd pldl1keep, p0, [x0, z0.s, sxtw #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x60,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 60 84 <unknown>
|
||||
|
||||
prfd pldl1keep, p0, [x0, z0.d, uxtw #3]
|
||||
// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, uxtw #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x20,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 20 c4 <unknown>
|
||||
|
||||
prfd pldl1keep, p0, [x0, z0.d, sxtw #3]
|
||||
// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, sxtw #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x60,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 60 c4 <unknown>
|
||||
|
||||
prfd pldl1keep, p0, [x0, z0.d, lsl #3]
|
||||
// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, lsl #3]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x60,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 e0 60 c4 <unknown>
|
||||
|
||||
prfd #15, p7, [z31.s, #0]
|
||||
// CHECK-INST: prfd #15, p7, [z31.s]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x80,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 80 85 <unknown>
|
||||
|
||||
prfd #15, p7, [z31.s, #248]
|
||||
// CHECK-INST: prfd #15, p7, [z31.s, #248]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x9f,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 9f 85 <unknown>
|
||||
|
||||
prfd #15, p7, [z31.d, #0]
|
||||
// CHECK-INST: prfd #15, p7, [z31.d]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x80,0xc5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 80 c5 <unknown>
|
||||
|
||||
prfd #15, p7, [z31.d, #248]
|
||||
// CHECK-INST: prfd #15, p7, [z31.d, #248]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x9f,0xc5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 9f c5 <unknown>
|
||||
|
||||
@ -26,7 +26,7 @@ prfh #pldl1keep, p0, [x0]
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid addressing modes
|
||||
// invalid scalar + scalar addressing modes
|
||||
|
||||
prfh #0, p0, [x0, #-33, mul vl]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
|
||||
@ -54,6 +54,98 @@ prfh #0, p0, [x0, x0, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + vector addressing modes
|
||||
|
||||
prfh #0, p0, [x0, z0.h]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.h]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.s]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.s]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.s]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.s]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.s, uxtw #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.s, lsl #1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.d, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.d, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [x0, z0.d, sxtw #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
|
||||
// CHECK-NEXT: prfh #0, p0, [x0, z0.d, sxtw #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector + immediate addressing modes
|
||||
|
||||
prfh #0, p0, [z0.s, #-2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.s, #-2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.s, #-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.s, #-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.s, #63]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.s, #63]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.s, #64]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.s, #64]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.s, #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.s, #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.d, #-2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.d, #-2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.d, #-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.d, #-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.d, #63]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.d, #63]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.d, #64]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.d, #64]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfh #0, p0, [z0.d, #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
|
||||
// CHECK-NEXT: prfh #0, p0, [z0.d, #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
|
||||
@ -192,3 +192,57 @@ prfh pldl1strm, p0, [x0, #31, mul vl]
|
||||
// CHECK-ENCODING: [0x01,0x20,0xdf,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 01 20 df 85
|
||||
|
||||
prfh pldl3strm, p5, [x10, z21.s, uxtw #1]
|
||||
// CHECK-INST: prfh pldl3strm, p5, [x10, z21.s, uxtw #1]
|
||||
// CHECK-ENCODING: [0x45,0x35,0x35,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 35 35 84 <unknown>
|
||||
|
||||
prfh pldl3strm, p5, [x10, z21.s, sxtw #1]
|
||||
// CHECK-INST: prfh pldl3strm, p5, [x10, z21.s, sxtw #1]
|
||||
// CHECK-ENCODING: [0x45,0x35,0x75,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 35 75 84 <unknown>
|
||||
|
||||
prfh pldl3strm, p5, [x10, z21.d, uxtw #1]
|
||||
// CHECK-INST: prfh pldl3strm, p5, [x10, z21.d, uxtw #1]
|
||||
// CHECK-ENCODING: [0x45,0x35,0x35,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 35 35 c4 <unknown>
|
||||
|
||||
prfh pldl3strm, p5, [x10, z21.d, sxtw #1]
|
||||
// CHECK-INST: prfh pldl3strm, p5, [x10, z21.d, sxtw #1]
|
||||
// CHECK-ENCODING: [0x45,0x35,0x75,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 35 75 c4 <unknown>
|
||||
|
||||
prfh pldl1keep, p0, [x0, z0.d, lsl #1]
|
||||
// CHECK-INST: prfh pldl1keep, p0, [x0, z0.d, lsl #1]
|
||||
// CHECK-ENCODING: [0x00,0xa0,0x60,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 a0 60 c4 <unknown>
|
||||
|
||||
prfh #15, p7, [z31.s, #0]
|
||||
// CHECK-INST: prfh #15, p7, [z31.s]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x80,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 80 84 <unknown>
|
||||
|
||||
prfh #15, p7, [z31.s, #62]
|
||||
// CHECK-INST: prfh #15, p7, [z31.s, #62]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x9f,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 9f 84 <unknown>
|
||||
|
||||
prfh #15, p7, [z31.d, #0]
|
||||
// CHECK-INST: prfh #15, p7, [z31.d]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x80,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 80 c4 <unknown>
|
||||
|
||||
prfh #15, p7, [z31.d, #62]
|
||||
// CHECK-INST: prfh #15, p7, [z31.d, #62]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x9f,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 9f c4 <unknown>
|
||||
|
||||
@ -26,7 +26,7 @@ prfw #pldl1keep, p0, [x0]
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid addressing modes
|
||||
// invalid scalar + scalar addressing modes
|
||||
|
||||
prfw #0, p0, [x0, #-33, mul vl]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
|
||||
@ -54,6 +54,99 @@ prfw #0, p0, [x0, x0, lsl #1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + vector addressing modes
|
||||
|
||||
prfw #0, p0, [x0, z0.h]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.h]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.s]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.s]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.s]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.s]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.s, uxtw #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.s, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.d, lsl #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.d, lsl #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [x0, z0.d, sxtw #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
|
||||
// CHECK-NEXT: prfw #0, p0, [x0, z0.d, sxtw #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid vector + immediate addressing modes
|
||||
|
||||
prfw #0, p0, [z0.s, #-4]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.s, #-4]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.s, #-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.s, #-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.s, #125]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.s, #125]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.s, #128]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.s, #128]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.s, #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.s, #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.d, #-4]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.d, #-4]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.d, #-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.d, #-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.d, #125]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.d, #125]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.d, #128]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.d, #128]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
prfw #0, p0, [z0.d, #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
|
||||
// CHECK-NEXT: prfw #0, p0, [z0.d, #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// invalid predicate
|
||||
|
||||
|
||||
@ -192,3 +192,57 @@ prfw pldl1strm, p0, [x0, #31, mul vl]
|
||||
// CHECK-ENCODING: [0x01,0x40,0xdf,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 01 40 df 85
|
||||
|
||||
prfw pldl1keep, p0, [x0, z0.s, uxtw #2]
|
||||
// CHECK-INST: prfw pldl1keep, p0, [x0, z0.s, uxtw #2]
|
||||
// CHECK-ENCODING: [0x00,0x40,0x20,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 40 20 84 <unknown>
|
||||
|
||||
prfw pldl3strm, p5, [x10, z21.s, sxtw #2]
|
||||
// CHECK-INST: prfw pldl3strm, p5, [x10, z21.s, sxtw #2]
|
||||
// CHECK-ENCODING: [0x45,0x55,0x75,0x84]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 55 75 84 <unknown>
|
||||
|
||||
prfw #7, p3, [x13, z8.d, uxtw #2]
|
||||
// CHECK-INST: prfw #7, p3, [x13, z8.d, uxtw #2]
|
||||
// CHECK-ENCODING: [0xa7,0x4d,0x28,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: a7 4d 28 c4 <unknown>
|
||||
|
||||
prfw pldl1keep, p0, [x0, z0.d, sxtw #2]
|
||||
// CHECK-INST: prfw pldl1keep, p0, [x0, z0.d, sxtw #2]
|
||||
// CHECK-ENCODING: [0x00,0x40,0x60,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 40 60 c4 <unknown>
|
||||
|
||||
prfw pldl3strm, p5, [x10, z21.d, lsl #2]
|
||||
// CHECK-INST: prfw pldl3strm, p5, [x10, z21.d, lsl #2]
|
||||
// CHECK-ENCODING: [0x45,0xd5,0x75,0xc4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 45 d5 75 c4 <unknown>
|
||||
|
||||
prfw #15, p7, [z31.s, #0]
|
||||
// CHECK-INST: prfw #15, p7, [z31.s]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x00,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 00 85 <unknown>
|
||||
|
||||
prfw #15, p7, [z31.s, #124]
|
||||
// CHECK-INST: prfw #15, p7, [z31.s, #124]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x1f,0x85]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 1f 85 <unknown>
|
||||
|
||||
prfw #15, p7, [z31.d, #0]
|
||||
// CHECK-INST: prfw #15, p7, [z31.d]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x00,0xc5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 00 c5 <unknown>
|
||||
|
||||
prfw #15, p7, [z31.d, #124]
|
||||
// CHECK-INST: prfw #15, p7, [z31.d, #124]
|
||||
// CHECK-ENCODING: [0xef,0xff,0x1f,0xc5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ef ff 1f c5 <unknown>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user