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Add some x86 specific dagcombines for conditional increments.
(add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y
for
unsigned foo(unsigned a, unsigned b) {
if (a == 0) b++;
return b;
}
we now get:
foo:
cmpl $1, %edi
movl %esi, %eax
adcl $0, %eax
ret
instead of:
foo:
testl %edi, %edi
sete %al
movzbl %al, %eax
addl %esi, %eax
ret
llvm-svn: 122364
This commit is contained in:
Benjamin Kramer
parent
fd119319ea
commit
369872edfc
@ -969,6 +969,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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if (Subtarget->is64Bit())
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@ -11513,6 +11515,44 @@ static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// fold (add Y, (sete X, 0)) -> adc 0, Y
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// (add Y, (setne X, 0)) -> sbb -1, Y
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// (sub (sete X, 0), Y) -> sbb 0, Y
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// (sub (setne X, 0), Y) -> adc -1, Y
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static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
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DebugLoc DL = N->getDebugLoc();
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// Look through ZExts.
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SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
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if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
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return SDValue();
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SDValue SetCC = Ext.getOperand(0);
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if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
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return SDValue();
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X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
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if (CC != X86::COND_E && CC != X86::COND_NE)
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return SDValue();
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SDValue Cmp = SetCC.getOperand(1);
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if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
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!X86::isZeroNode(Cmp.getOperand(1)))
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return SDValue();
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SDValue CmpOp0 = Cmp.getOperand(0);
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SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
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DAG.getConstant(1, CmpOp0.getValueType()));
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SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
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if (CC == X86::COND_NE)
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return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
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DL, OtherVal.getValueType(), OtherVal,
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DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
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return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
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DL, OtherVal.getValueType(), OtherVal,
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DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
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}
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SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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@ -11523,6 +11563,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
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case ISD::ADD:
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case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
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case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
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case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
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case ISD::SHL:
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89
test/CodeGen/X86/conditional-indecrement.ll
Normal file
89
test/CodeGen/X86/conditional-indecrement.ll
Normal file
@ -0,0 +1,89 @@
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; RUN: llc -march=x86 < %s | FileCheck %s
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define i32 @test1(i32 %a, i32 %b) nounwind readnone {
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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; CHECK: test1:
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; CHECK: cmpl $1
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; CHECK: sbbl $-1
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; CHECK: ret
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}
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define i32 @test2(i32 %a, i32 %b) nounwind readnone {
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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; CHECK: test2:
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; CHECK: cmpl $1
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; CHECK: adcl $0
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; CHECK: ret
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}
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define i32 @test3(i32 %a, i32 %b) nounwind readnone {
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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; CHECK: test3:
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; CHECK: cmpl $1
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; CHECK: adcl $0
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; CHECK: ret
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}
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define i32 @test4(i32 %a, i32 %b) nounwind readnone {
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = add i32 %inc, %b
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ret i32 %retval.0
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; CHECK: test4:
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; CHECK: cmpl $1
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; CHECK: sbbl $-1
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; CHECK: ret
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}
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define i32 @test5(i32 %a, i32 %b) nounwind readnone {
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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; CHECK: test5:
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; CHECK: cmpl $1
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; CHECK: adcl $-1
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; CHECK: ret
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}
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define i32 @test6(i32 %a, i32 %b) nounwind readnone {
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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; CHECK: test6:
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; CHECK: cmpl $1
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; CHECK: sbbl $0
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; CHECK: ret
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}
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define i32 @test7(i32 %a, i32 %b) nounwind readnone {
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%cmp = icmp eq i32 %a, 0
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%inc = zext i1 %cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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; CHECK: test7:
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; CHECK: cmpl $1
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; CHECK: sbbl $0
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; CHECK: ret
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}
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define i32 @test8(i32 %a, i32 %b) nounwind readnone {
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%not.cmp = icmp ne i32 %a, 0
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%inc = zext i1 %not.cmp to i32
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%retval.0 = sub i32 %b, %inc
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ret i32 %retval.0
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; CHECK: test8:
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; CHECK: cmpl $1
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; CHECK: adcl $-1
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; CHECK: ret
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}
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