From 36cd99ffe9deee2643a77b85ff3104dc9af4e487 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Thu, 26 Apr 2018 16:06:34 +0000 Subject: [PATCH] [mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952 --- lib/Target/Mips/MicroMipsInstrFormats.td | 2 +- lib/Target/Mips/MicroMipsInstrInfo.td | 30 +++++++------ lib/Target/Mips/MipsInstrInfo.td | 43 ++++++++----------- test/MC/Mips/micromips-control-instructions.s | 19 ++++++-- test/MC/Mips/mips-control-instructions.s | 20 ++++++--- 5 files changed, 65 insertions(+), 49 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFormats.td b/lib/Target/Mips/MicroMipsInstrFormats.td index 4e84ee3a3e7..050f8ba1e47 100644 --- a/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/lib/Target/Mips/MicroMipsInstrFormats.td @@ -630,7 +630,7 @@ class SYS_FM_MM : MMArch { let Inst{5-0} = 0x3c; } -class WAIT_FM_MM { +class WAIT_FM_MM : MMArch { bits<10> code_; bits<32> Inst; diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index d2768cd75d7..3e560f5e576 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -967,17 +967,18 @@ let DecoderNamespace = "MicroMips" in { let DecoderMethod = "DecodeSyncI_MM" in def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; - let Predicates = [InMicroMips] in { - def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; - def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM; - def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; - def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>; - def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>; + def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS; + def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM, + ISA_MICROMIPS; + def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS; + def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>, + ISA_MICROMIPS; + def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>, + ISA_MICROMIPS; def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>, - ISA_MIPS32R2; + ISA_MICROMIPS; def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>, - ISA_MIPS32R2; - } + ISA_MICROMIPS; /// Trap Instructions def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>, @@ -1174,11 +1175,11 @@ let Predicates = [InMicroMips] in { def UDIV_MM_Pseudo : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; - def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; + def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS; def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>; - def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; - def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2; + def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS; + def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS; def : MipsInstAlias<"teq $rs, $rt", (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tge $rs, $rt", @@ -1223,7 +1224,7 @@ let Predicates = [InMicroMips] in { (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; def : MipsInstAlias<"rotr $rt, $imm", (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; - def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; + def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS; def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS; @@ -1257,4 +1258,7 @@ let Predicates = [InMicroMips] in { ISA_MIPS32R2_NOT_32R6_64R6; def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, ISA_MIPS32R2_NOT_32R6_64R6; + def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS; + def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>, + ISA_MICROMIPS; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 25299723dbf..3ee92826ee7 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -2083,28 +2083,24 @@ let AdditionalPredicates = [NotInMicroMips] in { } let AdditionalPredicates = [NotInMicroMips] in { -def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; -def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>; -} -def TRAP : TrapBase; -let AdditionalPredicates = [NotInMicroMips] in { -def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; -} + def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1; + def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>, + ISA_MIPS1; + def TRAP : TrapBase, ISA_MIPS1; + def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, + ISA_MIPS32_NOT_32R6_64R6; -let AdditionalPredicates = [NotInMicroMips] in { def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32; - def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, ISA_MIPS32R5; + def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, + ISA_MIPS32R5; def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32; -} -let AdditionalPredicates = [NotInMicroMips] in { - def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, ISA_MIPS32R2; - def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, ISA_MIPS32R2; -} + def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, + ISA_MIPS32R2; + def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, + ISA_MIPS32R2; -let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug - AdditionalPredicates = [NotInMicroMips] in { -def WAIT : WAIT_FT<"wait">, WAIT_FM; + def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32; } let AdditionalPredicates = [NotInMicroMips] in { @@ -2116,7 +2112,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6; /// Jump and Branch Instructions def J : MMRel, JumpFJ, FJ<2>, AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch; -def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; +def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>, BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; @@ -2589,16 +2585,13 @@ def : MipsInstAlias<"beqz $rs,$offset", def : MipsInstAlias<"beqzl $rs,$offset", (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; let AdditionalPredicates = [NotInMicroMips] in { - def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; -} + def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1; -def : MipsInstAlias<"break", (BREAK 0, 0), 1>; -def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; -let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1; + def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1; def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; -} -let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; def : MipsInstAlias<"tge $rs, $rt", diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index a8964bfec89..e4946be5c34 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \ # RUN: | FileCheck -check-prefix=CHECK-EL %s -# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \ +# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \ # RUN: | FileCheck -check-prefix=CHECK-EB %s # Check that the assembler can handle the documented syntax # for control instructions. @@ -21,20 +21,31 @@ # CHECK-EL: ehb # encoding: [0x00,0x00,0x00,0x18] # CHECK-EL: pause # encoding: [0x00,0x00,0x00,0x28] # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00] +# CHECK-EL-NEXT: #