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[SelectionDAGBuilder] Add SPF_NABS support to visitSelect
We currently don't match this which limits the effectiveness of D91120 until InstCombine starts canonicalizing to llvm.abs. This should be easy to remove if/when we remove the SPF_ABS handling. Differential Revision: https://reviews.llvm.org/D92118
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@ -3131,6 +3131,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
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Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
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bool IsUnaryAbs = false;
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bool Negate = false;
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SDNodeFlags Flags;
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if (auto *FPOp = dyn_cast<FPMathOperator>(&I))
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@ -3195,12 +3196,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
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break;
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}
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break;
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case SPF_NABS:
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Negate = true;
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LLVM_FALLTHROUGH;
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case SPF_ABS:
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IsUnaryAbs = true;
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Opc = ISD::ABS;
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break;
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case SPF_NABS:
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// TODO: we need to produce sub(0, abs(X)).
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default: break;
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}
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@ -3227,10 +3229,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
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if (IsUnaryAbs) {
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for (unsigned i = 0; i != NumValues; ++i) {
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SDLoc dl = getCurSDLoc();
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EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i);
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Values[i] =
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DAG.getNode(OpCode, getCurSDLoc(),
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LHSVal.getNode()->getValueType(LHSVal.getResNo() + i),
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SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
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DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i));
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if (Negate)
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Values[i] = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT),
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Values[i]);
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}
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} else {
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for (unsigned i = 0; i != NumValues; ++i) {
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@ -111,26 +111,18 @@ define i64 @f3(i64 %x, i64 %y) {
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define i64 @f4(i64 %x) {
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; CHECK-LE-LABEL: f4:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: cmpdi r3, 0
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; CHECK-LE-NEXT: iselgt r3, r4, r3
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: cmplwi r3, 0
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; CHECK-32-NEXT: cmpwi cr1, r3, 0
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; CHECK-32-NEXT: crandc 4*cr5+lt, 4*cr1+gt, eq
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; CHECK-32-NEXT: cmpwi cr1, r4, 0
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; CHECK-32-NEXT: subfic r5, r4, 0
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; CHECK-32-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq
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; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
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; CHECK-32-NEXT: subfze r6, r3
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; CHECK-32-NEXT: bc 12, 4*cr5+lt, .LBB4_1
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB4_1:
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; CHECK-32-NEXT: addi r3, r6, 0
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; CHECK-32-NEXT: addi r4, r5, 0
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp sgt i64 %x, 0
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%x.neg = sub i64 0, %x
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@ -166,20 +158,18 @@ define i64 @f4_sge_0(i64 %x) {
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define i64 @f4_slt_0(i64 %x) {
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; CHECK-LE-LABEL: f4_slt_0:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: cmpdi r3, 0
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; CHECK-LE-NEXT: isellt r3, r3, r4
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_slt_0:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: subfic r5, r4, 0
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; CHECK-32-NEXT: subfze r6, r3
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; CHECK-32-NEXT: cmpwi r3, 0
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; CHECK-32-NEXT: bclr 12, lt, 0
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r3, r6, 0
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; CHECK-32-NEXT: ori r4, r5, 0
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp slt i64 %x, 0
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%x.neg = sub i64 0, %x
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@ -219,21 +209,18 @@ define i64 @f4_sle_0(i64 %x) {
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define i64 @f4_sgt_m1(i64 %x) {
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; CHECK-LE-LABEL: f4_sgt_m1:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: cmpdi r3, -1
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; CHECK-LE-NEXT: iselgt r3, r4, r3
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_sgt_m1:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: subfic r5, r4, 0
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; CHECK-32-NEXT: subfze r6, r3
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; CHECK-32-NEXT: cmpwi r3, -1
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; CHECK-32-NEXT: bc 12, gt, .LBB8_1
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB8_1:
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; CHECK-32-NEXT: addi r3, r6, 0
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; CHECK-32-NEXT: addi r4, r5, 0
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp sgt i64 %x, -1
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%x.neg = sub i64 0, %x
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@ -27,19 +27,16 @@ define i32 @neg_abs32(i32 %x) {
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define i32 @select_neg_abs32(i32 %x) {
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; RV32-LABEL: select_neg_abs32:
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; RV32: # %bb.0:
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; RV32-NEXT: bltz a0, .LBB1_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: srai a1, a0, 31
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: sub a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_neg_abs32:
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; RV64: # %bb.0:
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; RV64-NEXT: sext.w a1, a0
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; RV64-NEXT: bltz a1, .LBB1_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: negw a0, a0
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: sraiw a1, a0, 31
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: subw a0, a1, a0
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; RV64-NEXT: ret
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%1 = icmp slt i32 %x, 0
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%2 = sub nsw i32 0, %x
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@ -73,21 +70,20 @@ define i64 @neg_abs64(i64 %x) {
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define i64 @select_neg_abs64(i64 %x) {
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; RV32-LABEL: select_neg_abs64:
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; RV32: # %bb.0:
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; RV32-NEXT: bltz a1, .LBB3_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: snez a2, a0
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: neg a1, a1
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; RV32-NEXT: neg a0, a0
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; RV32-NEXT: .LBB3_2:
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; RV32-NEXT: srai a2, a1, 31
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; RV32-NEXT: xor a0, a0, a2
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; RV32-NEXT: sltu a3, a2, a0
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; RV32-NEXT: xor a1, a1, a2
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; RV32-NEXT: sub a1, a2, a1
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; RV32-NEXT: sub a1, a1, a3
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; RV32-NEXT: sub a0, a2, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: select_neg_abs64:
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; RV64: # %bb.0:
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; RV64-NEXT: bltz a0, .LBB3_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: neg a0, a0
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; RV64-NEXT: .LBB3_2:
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; RV64-NEXT: srai a1, a0, 63
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: sub a0, a1, a0
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; RV64-NEXT: ret
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%1 = icmp slt i64 %x, 0
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%2 = sub nsw i64 0, %x
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