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[AMDGPU] Allow some modifiers on VOP3B instructions
V_DIV_SCALE_F32/F64 are VOP3B encoded so they can't use the ABS src modifier, but they can still use NEG and the usual output modifiers. This partially reverts 3b99f12a4e6f "AMDGPU: Remove modifiers from v_div_scale_*". Differential Revision: https://reviews.llvm.org/D90296
This commit is contained in:
Jay Foad
parent
5e1af7e742
commit
36faa379a8
@ -256,11 +256,15 @@ private:
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bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
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bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const;
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bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods,
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bool AllowAbs = true) const;
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3BMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
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bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp, SDValue &Omod) const;
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bool SelectVOP3BMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp, SDValue &Omod) const;
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bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
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SDValue &Clamp, SDValue &Omod) const;
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@ -1129,7 +1133,12 @@ void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
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unsigned Opc
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= (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
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// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
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// omod
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SDValue Ops[8];
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SelectVOP3BMods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
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SelectVOP3BMods(N->getOperand(1), Ops[3], Ops[2]);
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SelectVOP3BMods(N->getOperand(2), Ops[5], Ops[4]);
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CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
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}
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@ -2630,7 +2639,8 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(SDNode *N) {
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
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unsigned &Mods) const {
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unsigned &Mods,
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bool AllowAbs) const {
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Mods = 0;
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Src = In;
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@ -2639,7 +2649,7 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
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Src = Src.getOperand(0);
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}
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if (Src.getOpcode() == ISD::FABS) {
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if (AllowAbs && Src.getOpcode() == ISD::FABS) {
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Mods |= SISrcMods::ABS;
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Src = Src.getOperand(0);
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}
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@ -2658,6 +2668,17 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3BMods(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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unsigned Mods;
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if (SelectVOP3ModsImpl(In, Src, Mods, /* AllowAbs */ false)) {
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SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
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return true;
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}
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
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SDValue &SrcMods) const {
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SelectVOP3Mods(In, Src, SrcMods);
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@ -2682,6 +2703,16 @@ bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
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return SelectVOP3Mods(In, Src, SrcMods);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3BMods0(SDValue In, SDValue &Src,
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SDValue &SrcMods, SDValue &Clamp,
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SDValue &Omod) const {
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SDLoc DL(In);
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Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
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Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);
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return SelectVOP3BMods(In, Src, SrcMods);
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}
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bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
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SDValue &Clamp, SDValue &Omod) const {
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Src = In;
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@ -871,6 +871,8 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
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else
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return false;
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// TODO: Match source modifiers.
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock *MBB = MI.getParent();
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@ -882,9 +884,14 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
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auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
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.addDef(Dst1)
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.addUse(Src0)
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.addUse(Denom)
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.addUse(Numer);
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.addImm(0) // $src0_modifiers
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.addUse(Src0) // $src0
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.addImm(0) // $src1_modifiers
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.addUse(Denom) // $src1
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.addImm(0) // $src2_modifiers
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.addUse(Numer) // $src2
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.addImm(0) // $clamp
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.addImm(0); // $omod
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MI.eraseFromParent();
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return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
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@ -3157,7 +3164,8 @@ AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const {
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}
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std::pair<Register, unsigned>
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AMDGPUInstructionSelector::selectVOP3ModsImpl(MachineOperand &Root) const {
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AMDGPUInstructionSelector::selectVOP3ModsImpl(MachineOperand &Root,
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bool AllowAbs) const {
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Register Src = Root.getReg();
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Register OrigSrc = Src;
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unsigned Mods = 0;
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@ -3169,7 +3177,7 @@ AMDGPUInstructionSelector::selectVOP3ModsImpl(MachineOperand &Root) const {
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MI = getDefIgnoringCopies(Src, *MRI);
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}
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if (MI && MI->getOpcode() == AMDGPU::G_FABS) {
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if (AllowAbs && MI && MI->getOpcode() == AMDGPU::G_FABS) {
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Src = MI->getOperand(1).getReg();
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Mods |= SISrcMods::ABS;
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}
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@ -3215,6 +3223,20 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3BMods0(MachineOperand &Root) const {
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /* AllowAbs */ false);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }, // src0_mods
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
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[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3OMods(MachineOperand &Root) const {
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return {{
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@ -3236,6 +3258,18 @@ AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3BMods(MachineOperand &Root) const {
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Register Src;
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unsigned Mods;
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std::tie(Src, Mods) = selectVOP3ModsImpl(Root, /* AllowAbs */ false);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
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}};
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}
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InstructionSelector::ComplexRendererFns
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AMDGPUInstructionSelector::selectVOP3NoMods(MachineOperand &Root) const {
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Register Reg = Root.getReg();
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@ -145,8 +145,8 @@ private:
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bool selectGlobalAtomicFaddIntrinsic(MachineInstr &I) const;
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bool selectBVHIntrinsic(MachineInstr &I) const;
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std::pair<Register, unsigned>
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selectVOP3ModsImpl(MachineOperand &Root) const;
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std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
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bool AllowAbs = true) const;
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InstructionSelector::ComplexRendererFns
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selectVCSRC(MachineOperand &Root) const;
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@ -157,9 +157,13 @@ private:
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3BMods0(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3OMods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3Mods(MachineOperand &Root) const;
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InstructionSelector::ComplexRendererFns
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selectVOP3BMods(MachineOperand &Root) const;
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ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
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@ -1369,6 +1369,7 @@ private:
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bool validateVccOperand(unsigned Reg) const;
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bool validateVOP3Literal(const MCInst &Inst) const;
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bool validateMAIAccWrite(const MCInst &Inst);
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bool validateDivScale(const MCInst &Inst);
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unsigned getConstantBusLimit(unsigned Opcode) const;
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bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
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bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
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@ -3304,6 +3305,35 @@ bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst) {
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return true;
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}
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bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
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switch (Inst.getOpcode()) {
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default:
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return true;
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case V_DIV_SCALE_F32_gfx6_gfx7:
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case V_DIV_SCALE_F32_vi:
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case V_DIV_SCALE_F32_gfx10:
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case V_DIV_SCALE_F64_gfx6_gfx7:
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case V_DIV_SCALE_F64_vi:
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case V_DIV_SCALE_F64_gfx10:
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break;
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}
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// TODO: Check that src0 = src1 or src2.
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for (auto Name : {AMDGPU::OpName::src0_modifiers,
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AMDGPU::OpName::src2_modifiers,
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AMDGPU::OpName::src2_modifiers}) {
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if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))
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.getImm() &
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SISrcMods::ABS) {
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Error(getLoc(), "ABS not allowed in VOP3B instructions");
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return false;
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}
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}
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return true;
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}
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bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
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const unsigned Opc = Inst.getOpcode();
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@ -3777,6 +3807,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
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if (!validateMAIAccWrite(Inst)) {
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return false;
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}
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if (!validateDivScale(Inst)) {
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return false;
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}
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return true;
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}
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@ -11085,9 +11085,9 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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// Satisfy the operand register constraint when one of the inputs is
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// undefined. Ordinarily each undef value will have its own implicit_def of
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// a vreg, so force these to use a single register.
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SDValue Src0 = Node->getOperand(0);
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SDValue Src1 = Node->getOperand(1);
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SDValue Src2 = Node->getOperand(2);
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SDValue Src0 = Node->getOperand(1);
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SDValue Src1 = Node->getOperand(3);
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SDValue Src2 = Node->getOperand(5);
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if ((Src0.isMachineOpcode() &&
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Src0.getMachineOpcode() != AMDGPU::IMPLICIT_DEF) &&
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@ -11122,10 +11122,10 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
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} else
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break;
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SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };
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for (unsigned I = 3, N = Node->getNumOperands(); I != N; ++I)
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Ops.push_back(Node->getOperand(I));
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SmallVector<SDValue, 9> Ops(Node->op_begin(), Node->op_end());
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Ops[1] = Src0;
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Ops[3] = Src1;
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Ops[5] = Src2;
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Ops.push_back(ImpDef.getValue(1));
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return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
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}
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@ -3887,6 +3887,15 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
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return false;
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}
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}
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if ((getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm() &
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SISrcMods::ABS) ||
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(getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm() &
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SISrcMods::ABS) ||
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(getNamedOperand(MI, AMDGPU::OpName::src2_modifiers)->getImm() &
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SISrcMods::ABS)) {
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ErrInfo = "ABS not allowed in VOP3B instructions";
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return false;
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}
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}
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if (isSOP2(MI) || isSOPC(MI)) {
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@ -193,12 +193,8 @@ class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProf
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}
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class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
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// v_div_scale_{f32|f64} do not support input modifiers.
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let HasModifiers = 0;
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let HasClamp = 0;
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let HasOMod = 0;
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let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
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let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
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let Asm64 = " $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
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}
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def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
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@ -388,13 +384,11 @@ def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPU
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let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
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def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
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let SchedRW = [WriteFloatFMA, WriteSALU];
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let AsmMatchConverter = "";
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}
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// Double precision division pre-scale.
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def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
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let SchedRW = [WriteDouble, WriteSALU];
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let AsmMatchConverter = "";
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let FPDPRounding = 1;
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}
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} // End mayRaiseFPException = 0
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@ -11,8 +11,8 @@ define float @fdiv_f32(float %a, float %b) #0 {
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: %6:vgpr_32, %7:sreg_64 = nofpexcept V_DIV_SCALE_F32 [[COPY2]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
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; GCN: %8:vgpr_32, %9:sreg_64 = nofpexcept V_DIV_SCALE_F32 [[COPY1]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
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; GCN: %6:vgpr_32, %7:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, [[COPY2]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: %8:vgpr_32, %9:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, [[COPY1]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: %10:vgpr_32 = nofpexcept V_RCP_F32_e64 0, %8, 0, 0, implicit $mode, implicit $exec
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
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@ -44,8 +44,8 @@ define float @fdiv_nnan_f32(float %a, float %b) #0 {
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: %6:vgpr_32, %7:sreg_64 = nnan nofpexcept V_DIV_SCALE_F32 [[COPY2]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
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; GCN: %8:vgpr_32, %9:sreg_64 = nnan nofpexcept V_DIV_SCALE_F32 [[COPY1]], [[COPY1]], [[COPY2]], implicit $mode, implicit $exec
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; GCN: %6:vgpr_32, %7:sreg_64 = nnan nofpexcept V_DIV_SCALE_F32 0, [[COPY2]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: %8:vgpr_32, %9:sreg_64 = nnan nofpexcept V_DIV_SCALE_F32 0, [[COPY1]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
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; GCN: %10:vgpr_32 = nnan nofpexcept V_RCP_F32_e64 0, %8, 0, 0, implicit $mode, implicit $exec
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
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@ -55,7 +55,7 @@ body: |
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S_BRANCH %bb.3
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bb.3:
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$vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $mode, implicit $exec
|
||||
$vgpr4, $vcc = V_DIV_SCALE_F32 0, $vgpr1, 0, $vgpr1, 0, $vgpr3, 0, 0, implicit $mode, implicit $exec
|
||||
$vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
|
||||
@ -322,8 +322,7 @@ define amdgpu_kernel void @test_div_scale_f32_inline_imm_den(float addrspace(1)*
|
||||
; SI-LABEL: {{^}}test_div_scale_f32_fneg_num:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
|
||||
; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[NEG_A]]
|
||||
; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], -[[A]]
|
||||
; SI: buffer_store_dword [[RESULT0]]
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @test_div_scale_f32_fneg_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
|
||||
@ -368,8 +367,7 @@ define amdgpu_kernel void @test_div_scale_f32_fabs_num(float addrspace(1)* %out,
|
||||
; SI-LABEL: {{^}}test_div_scale_f32_fneg_den:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI: v_xor_b32_e32 [[NEG_B:v[0-9]+]], 0x80000000, [[B]]
|
||||
; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[NEG_B]], [[NEG_B]], [[A]]
|
||||
; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], -[[B]], -[[B]], [[A]]
|
||||
; SI: buffer_store_dword [[RESULT0]]
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @test_div_scale_f32_fneg_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
|
||||
|
||||
@ -288,9 +288,9 @@ body: |
|
||||
%87:vgpr_32 = IMPLICIT_DEF
|
||||
%88:vgpr_32 = IMPLICIT_DEF
|
||||
%90:vgpr_32 = IMPLICIT_DEF
|
||||
%91:vgpr_32, dead %92:sreg_64 = nofpexcept V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $mode, implicit $exec
|
||||
%91:vgpr_32, dead %92:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, %90, 0, %90, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
|
||||
%95:vgpr_32 = nofpexcept V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $mode, implicit $exec
|
||||
%96:vgpr_32, %97:sreg_64 = nofpexcept V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $mode, implicit $exec
|
||||
%96:vgpr_32, %97:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, 1065353216, 0, %90, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
|
||||
%98:vgpr_32 = IMPLICIT_DEF
|
||||
%99:vgpr_32 = IMPLICIT_DEF
|
||||
%100:vgpr_32 = IMPLICIT_DEF
|
||||
@ -299,11 +299,11 @@ body: |
|
||||
%103:vgpr_32 = IMPLICIT_DEF
|
||||
%104:vgpr_32 = IMPLICIT_DEF
|
||||
%105:vgpr_32 = IMPLICIT_DEF
|
||||
%106:vgpr_32, dead %107:sreg_64 = nofpexcept V_DIV_SCALE_F32 %90, %90, %105, implicit $mode, implicit $exec
|
||||
%106:vgpr_32, dead %107:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, %90, 0, %90, 0, %105, 0, 0, implicit $mode, implicit $exec
|
||||
%108:vgpr_32 = nofpexcept V_RCP_F32_e32 0, implicit $mode, implicit $exec
|
||||
%109:vgpr_32 = IMPLICIT_DEF
|
||||
%110:vgpr_32 = nofpexcept V_FMA_F32 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%111:vgpr_32, %112:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, 0, 0, implicit $mode, implicit $exec
|
||||
%111:vgpr_32, %112:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%113:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %110, implicit $mode, implicit $exec
|
||||
%114:vgpr_32 = IMPLICIT_DEF
|
||||
%115:vgpr_32 = IMPLICIT_DEF
|
||||
|
||||
@ -92,3 +92,13 @@ v_interp_p1ll_f16 v5, v2, attr31.x v0
|
||||
v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2
|
||||
// GFX67: error: instruction not supported on this GPU
|
||||
// GFX89: error: invalid operand for instruction
|
||||
|
||||
//
|
||||
// v_div_scale_*
|
||||
//
|
||||
|
||||
v_div_scale_f32 v24, vcc, v22, v22, |v20|
|
||||
// GCN: error: ABS not allowed in VOP3B instructions
|
||||
|
||||
v_div_scale_f64 v[24:25], vcc, -|v[22:23]|, v[22:23], v[20:21]
|
||||
// GCN: error: ABS not allowed in VOP3B instructions
|
||||
|
||||
@ -411,14 +411,34 @@ v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21]
|
||||
// SICI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xdc,0xd2,0x16,0x2d,0x52,0x04]
|
||||
// VI: v_div_scale_f64 v[24:25], vcc, v[22:23], v[22:23], v[20:21] ; encoding: [0x18,0x6a,0xe1,0xd1,0x16,0x2d,0x52,0x04]
|
||||
|
||||
v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21]
|
||||
// SICI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21] ; encoding: [0x18,0x0a,0xdc,0xd2,0x16,0x29,0x52,0x04]
|
||||
// VI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], v[20:21] ; encoding: [0x18,0x0a,0xe1,0xd1,0x16,0x29,0x52,0x04]
|
||||
v_div_scale_f64 v[24:25], s[10:11], -v[22:23], v[20:21], v[20:21] clamp
|
||||
// SICI: v_div_scale_f64 v[24:25], s[10:11], -v[22:23], v[20:21], v[20:21] clamp ; encoding: [0x18,0x0a,0xdc,0xd2,0x16,0x29,0x52,0x24]
|
||||
// VI: v_div_scale_f64 v[24:25], s[10:11], -v[22:23], v[20:21], v[20:21] clamp ; encoding: [0x18,0x8a,0xe1,0xd1,0x16,0x29,0x52,0x24]
|
||||
|
||||
v_div_scale_f64 v[24:25], s[10:11], v[22:23], -v[20:21], v[20:21] clamp mul:2
|
||||
// SICI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], -v[20:21], v[20:21] clamp mul:2 ; encoding: [0x18,0x0a,0xdc,0xd2,0x16,0x29,0x52,0x4c]
|
||||
// VI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], -v[20:21], v[20:21] clamp mul:2 ; encoding: [0x18,0x8a,0xe1,0xd1,0x16,0x29,0x52,0x4c]
|
||||
|
||||
v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], -v[20:21]
|
||||
// SICI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], -v[20:21] ; encoding: [0x18,0x0a,0xdc,0xd2,0x16,0x29,0x52,0x84]
|
||||
// VI: v_div_scale_f64 v[24:25], s[10:11], v[22:23], v[20:21], -v[20:21] ; encoding: [0x18,0x0a,0xe1,0xd1,0x16,0x29,0x52,0x84]
|
||||
|
||||
v_div_scale_f32 v24, vcc, v22, v22, v20
|
||||
// SICI: v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0x52,0x04]
|
||||
// VI: v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0x52,0x04]
|
||||
|
||||
v_div_scale_f32 v24, vcc, -v22, v22, v20
|
||||
// SICI: v_div_scale_f32 v24, vcc, -v22, v22, v20 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0x52,0x24]
|
||||
// VI: v_div_scale_f32 v24, vcc, -v22, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0x52,0x24]
|
||||
|
||||
v_div_scale_f32 v24, vcc, v22, -v22, v20 clamp
|
||||
// SICI: v_div_scale_f32 v24, vcc, v22, -v22, v20 clamp ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0x52,0x44]
|
||||
// VI: v_div_scale_f32 v24, vcc, v22, -v22, v20 clamp ; encoding: [0x18,0xea,0xe0,0xd1,0x16,0x2d,0x52,0x44]
|
||||
|
||||
v_div_scale_f32 v24, vcc, v22, v22, -v20 clamp div:2
|
||||
// SICI: v_div_scale_f32 v24, vcc, v22, v22, -v20 clamp div:2 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0x52,0x9c]
|
||||
// VI: v_div_scale_f32 v24, vcc, v22, v22, -v20 clamp div:2 ; encoding: [0x18,0xea,0xe0,0xd1,0x16,0x2d,0x52,0x9c]
|
||||
|
||||
v_div_scale_f32 v24, s[10:11], v22, v22, v20
|
||||
// SICI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xda,0xd2,0x16,0x2d,0x52,0x04]
|
||||
// VI: v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xe0,0xd1,0x16,0x2d,0x52,0x04]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user