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AArch64] Handle ISD::LRINT and ISD::LLRINT for float16

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This patch is a follow up for D62018 to add lrint/llrint
support for float16.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62863

llvm-svn: 362700
This commit is contained in:
Adhemerval Zanella 2019-06-06 12:38:11 +00:00
parent c33ba7a738
commit 37549aa093
4 changed files with 114 additions and 0 deletions
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8
lib/Target/AArch64/AArch64InstrInfo.td
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@ -3168,6 +3168,14 @@ let Predicates = [HasFRInt3264] in {
defm FRINT64X : FRIntNNT<0b11, "frint64x">;
} // HasFRInt3264
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (lrint f16:$Rn)),
(FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
def : Pat<(i64 (lrint f16:$Rn)),
(FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
def : Pat<(i64 (llrint f16:$Rn)),
(FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
}
def : Pat<(i32 (lrint f32:$Rn)),
(FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i32 (lrint f64:$Rn)),

35
test/CodeGen/AArch64/llrint-conv-fp16.ll Normal file
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@ -0,0 +1,35 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.llrint.i64.f16(half) nounwind readnone

36
test/CodeGen/AArch64/lrint-conv-fp16-win.ll Normal file
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@ -0,0 +1,36 @@
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = trunc i32 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs w8, h0
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
declare i32 @llvm.lrint.i32.f16(half) nounwind readnone

35
test/CodeGen/AArch64/lrint-conv-fp16.ll Normal file
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@ -0,0 +1,35 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: frintx h0, h0
; CHECK-NEXT: fcvtzs x0, h0
; CHECK: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.lrint.i64.f16(half) nounwind readnone