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Tabs -> spaces, and remove trailing whitespace.

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llvm-svn: 82355
This commit is contained in:
Daniel Dunbar 2009-09-20 02:20:51 +00:00
parent d402d7374a
commit 378331a13d
19 changed files with 1234 additions and 1235 deletions
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4
lib/Analysis/DebugInfo.cpp
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@ -793,7 +793,7 @@ DILexicalBlock DIFactory::CreateLexicalBlock(DIDescriptor Context) {
/// CreateLocation - Creates a debug info location.
DILocation DIFactory::CreateLocation(unsigned LineNo, unsigned ColumnNo,
DIScope S, DILocation OrigLoc) {
DIScope S, DILocation OrigLoc) {
Value *Elts[] = {
ConstantInt::get(Type::getInt32Ty(VMContext), LineNo),
ConstantInt::get(Type::getInt32Ty(VMContext), ColumnNo),
@ -1218,7 +1218,7 @@ namespace llvm {
// If this location is already tracked then use it.
DebugLocTuple Tuple(Context, Loc.getLineNumber(),
Loc.getColumnNumber());
Loc.getColumnNumber());
DenseMap<DebugLocTuple, unsigned>::iterator II
= DebugLocInfo.DebugIdMap.find(Tuple);
if (II != DebugLocInfo.DebugIdMap.end())

568
lib/AsmParser/LLParser.cpp
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File diff suppressed because it is too large Load Diff

412
lib/Bitcode/Reader/BitcodeReader.cpp
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File diff suppressed because it is too large Load Diff

274
lib/Bitcode/Writer/BitcodeWriter.cpp
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@ -34,19 +34,19 @@ using namespace llvm;
/// be kept in sync with the reader, but need to be consistent within this file.
enum {
CurVersion = 0,
// VALUE_SYMTAB_BLOCK abbrev id's.
VST_ENTRY_8_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
VST_ENTRY_7_ABBREV,
VST_ENTRY_6_ABBREV,
VST_BBENTRY_6_ABBREV,
// CONSTANTS_BLOCK abbrev id's.
CONSTANTS_SETTYPE_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
CONSTANTS_INTEGER_ABBREV,
CONSTANTS_CE_CAST_Abbrev,
CONSTANTS_NULL_Abbrev,
// FUNCTION_BLOCK abbrev id's.
FUNCTION_INST_LOAD_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
FUNCTION_INST_BINOP_ABBREV,
@ -102,24 +102,24 @@ static unsigned GetEncodedBinaryOpcode(unsigned Opcode) {
static void WriteStringRecord(unsigned Code, const std::string &Str,
static void WriteStringRecord(unsigned Code, const std::string &Str,
unsigned AbbrevToUse, BitstreamWriter &Stream) {
SmallVector<unsigned, 64> Vals;
// Code: [strchar x N]
for (unsigned i = 0, e = Str.size(); i != e; ++i)
Vals.push_back(Str[i]);
// Emit the finished record.
Stream.EmitRecord(Code, Vals, AbbrevToUse);
}
// Emit information about parameter attributes.
static void WriteAttributeTable(const ValueEnumerator &VE,
static void WriteAttributeTable(const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const std::vector<AttrListPtr> &Attrs = VE.getAttributes();
if (Attrs.empty()) return;
Stream.EnterSubblock(bitc::PARAMATTR_BLOCK_ID, 3);
SmallVector<uint64_t, 64> Record;
@ -140,21 +140,21 @@ static void WriteAttributeTable(const ValueEnumerator &VE,
Record.push_back(FauxAttr);
}
Stream.EmitRecord(bitc::PARAMATTR_CODE_ENTRY, Record);
Record.clear();
}
Stream.ExitBlock();
}
/// WriteTypeTable - Write out the type table for a module.
static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
const ValueEnumerator::TypeList &TypeList = VE.getTypes();
Stream.EnterSubblock(bitc::TYPE_BLOCK_ID, 4 /*count from # abbrevs */);
SmallVector<uint64_t, 64> TypeVals;
// Abbrev for TYPE_CODE_POINTER.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_POINTER));
@ -162,7 +162,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Log2_32_Ceil(VE.getTypes().size()+1)));
Abbv->Add(BitCodeAbbrevOp(0)); // Addrspace = 0
unsigned PtrAbbrev = Stream.EmitAbbrev(Abbv);
// Abbrev for TYPE_CODE_FUNCTION.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_FUNCTION));
@ -172,7 +172,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned FunctionAbbrev = Stream.EmitAbbrev(Abbv);
// Abbrev for TYPE_CODE_STRUCT.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_STRUCT));
@ -181,7 +181,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned StructAbbrev = Stream.EmitAbbrev(Abbv);
// Abbrev for TYPE_CODE_ARRAY.
Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::TYPE_CODE_ARRAY));
@ -189,18 +189,18 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed,
Log2_32_Ceil(VE.getTypes().size()+1)));
unsigned ArrayAbbrev = Stream.EmitAbbrev(Abbv);
// Emit an entry count so the reader can reserve space.
TypeVals.push_back(TypeList.size());
Stream.EmitRecord(bitc::TYPE_CODE_NUMENTRY, TypeVals);
TypeVals.clear();
// Loop over all of the types, emitting each in turn.
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
const Type *T = TypeList[i].first;
int AbbrevToUse = 0;
unsigned Code = 0;
switch (T->getTypeID()) {
default: llvm_unreachable("Unknown type!");
case Type::VoidTyID: Code = bitc::TYPE_CODE_VOID; break;
@ -274,7 +274,7 @@ static void WriteTypeTable(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Stream.EmitRecord(Code, TypeVals, AbbrevToUse);
TypeVals.clear();
}
Stream.ExitBlock();
}
@ -337,7 +337,7 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
GV != E; ++GV) {
MaxAlignment = std::max(MaxAlignment, GV->getAlignment());
MaxGlobalType = std::max(MaxGlobalType, VE.getTypeID(GV->getType()));
if (!GV->hasSection()) continue;
// Give section names unique ID's.
unsigned &Entry = SectionMap[GV->getSection()];
@ -367,10 +367,10 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
}
}
}
// Emit abbrev for globals, now that we know # sections and max alignment.
unsigned SimpleGVarAbbrev = 0;
if (!M->global_empty()) {
if (!M->global_empty()) {
// Add an abbrev for common globals with no visibility or thread localness.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::MODULE_CODE_GLOBALVAR));
@ -394,14 +394,14 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
// Don't bother emitting vis + thread local.
SimpleGVarAbbrev = Stream.EmitAbbrev(Abbv);
}
// Emit the global variable information.
SmallVector<unsigned, 64> Vals;
for (Module::const_global_iterator GV = M->global_begin(),E = M->global_end();
GV != E; ++GV) {
unsigned AbbrevToUse = 0;
// GLOBALVAR: [type, isconst, initid,
// GLOBALVAR: [type, isconst, initid,
// linkage, alignment, section, visibility, threadlocal]
Vals.push_back(VE.getTypeID(GV->getType()));
Vals.push_back(GV->isConstant());
@ -410,14 +410,14 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
Vals.push_back(getEncodedLinkage(GV));
Vals.push_back(Log2_32(GV->getAlignment())+1);
Vals.push_back(GV->hasSection() ? SectionMap[GV->getSection()] : 0);
if (GV->isThreadLocal() ||
if (GV->isThreadLocal() ||
GV->getVisibility() != GlobalValue::DefaultVisibility) {
Vals.push_back(getEncodedVisibility(GV));
Vals.push_back(GV->isThreadLocal());
} else {
AbbrevToUse = SimpleGVarAbbrev;
}
Stream.EmitRecord(bitc::MODULE_CODE_GLOBALVAR, Vals, AbbrevToUse);
Vals.clear();
}
@ -435,13 +435,13 @@ static void WriteModuleInfo(const Module *M, const ValueEnumerator &VE,
Vals.push_back(F->hasSection() ? SectionMap[F->getSection()] : 0);
Vals.push_back(getEncodedVisibility(F));
Vals.push_back(F->hasGC() ? GCMap[F->getGC()] : 0);
unsigned AbbrevToUse = 0;
Stream.EmitRecord(bitc::MODULE_CODE_FUNCTION, Vals, AbbrevToUse);
Vals.clear();
}
// Emit the alias information.
for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end();
AI != E; ++AI) {
@ -496,7 +496,7 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
unsigned MDSAbbrev = 0;
SmallVector<uint64_t, 64> Record;
for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
if (const MDNode *N = dyn_cast<MDNode>(Vals[i].first)) {
if (!StartedMetadataBlock) {
Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
@ -506,7 +506,7 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
} else if (const MDString *MDS = dyn_cast<MDString>(Vals[i].first)) {
if (!StartedMetadataBlock) {
Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
// Abbrev for METADATA_STRING.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::METADATA_STRING));
@ -515,12 +515,12 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
MDSAbbrev = Stream.EmitAbbrev(Abbv);
StartedMetadataBlock = true;
}
// Code: [strchar x N]
const char *StrBegin = MDS->begin();
for (unsigned i = 0, e = MDS->length(); i != e; ++i)
Record.push_back(StrBegin[i]);
// Emit the finished record.
Stream.EmitRecord(bitc::METADATA_STRING, Record, MDSAbbrev);
Record.clear();
@ -540,26 +540,26 @@ static void WriteModuleMetadata(const ValueEnumerator &VE,
// Write named metadata elements.
for (unsigned i = 0, e = NMD->getNumElements(); i != e; ++i) {
if (NMD->getElement(i))
if (NMD->getElement(i))
Record.push_back(VE.getValueID(NMD->getElement(i)));
else
else
Record.push_back(0);
}
Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0);
Record.clear();
}
}
if (StartedMetadataBlock)
Stream.ExitBlock();
}
static void WriteMetadataAttachment(const Function &F,
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
bool StartedMetadataBlock = false;
SmallVector<uint64_t, 64> Record;
// Write metadata attachments
// METADATA_ATTACHMENT - [m x [value, [n x [id, mdnode]]]
Metadata &TheMetadata = F.getContext().getMetadata();
@ -570,41 +570,41 @@ static void WriteMetadataAttachment(const Function &F,
if (!P) continue;
bool RecordedInstruction = false;
for (Metadata::MDMapTy::const_iterator PI = P->begin(), PE = P->end();
PI != PE; ++PI) {
if (MDNode *ND = dyn_cast_or_null<MDNode>(PI->second)) {
if (RecordedInstruction == false) {
Record.push_back(VE.getInstructionID(I));
RecordedInstruction = true;
}
Record.push_back(PI->first);
Record.push_back(VE.getValueID(ND));
}
PI != PE; ++PI) {
if (MDNode *ND = dyn_cast_or_null<MDNode>(PI->second)) {
if (RecordedInstruction == false) {
Record.push_back(VE.getInstructionID(I));
RecordedInstruction = true;
}
Record.push_back(PI->first);
Record.push_back(VE.getValueID(ND));
}
}
if (!StartedMetadataBlock) {
Stream.EnterSubblock(bitc::METADATA_ATTACHMENT_ID, 3);
StartedMetadataBlock = true;
Stream.EnterSubblock(bitc::METADATA_ATTACHMENT_ID, 3);
StartedMetadataBlock = true;
}
Stream.EmitRecord(bitc::METADATA_ATTACHMENT, Record, 0);
Record.clear();
}
if (StartedMetadataBlock)
if (StartedMetadataBlock)
Stream.ExitBlock();
}
static void WriteModuleMetadataStore(const Module *M,
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
bool StartedMetadataBlock = false;
SmallVector<uint64_t, 64> Record;
// Write metadata kinds
// METADATA_KIND - [n x [id, name]]
Metadata &TheMetadata = M->getContext().getMetadata();
const StringMap<unsigned> *Kinds = TheMetadata.getHandlerNames();
for (StringMap<unsigned>::const_iterator
I = Kinds->begin(), E = Kinds->end(); I != E; ++I) {
for (StringMap<unsigned>::const_iterator
I = Kinds->begin(), E = Kinds->end(); I != E; ++I) {
Record.push_back(I->second);
StringRef KName = I->first();
for (unsigned i = 0, e = KName.size(); i != e; ++i)
@ -617,7 +617,7 @@ static void WriteModuleMetadataStore(const Module *M,
Record.clear();
}
if (StartedMetadataBlock)
if (StartedMetadataBlock)
Stream.ExitBlock();
}
@ -625,7 +625,7 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
const ValueEnumerator &VE,
BitstreamWriter &Stream, bool isGlobal) {
if (FirstVal == LastVal) return;
Stream.EnterSubblock(bitc::CONSTANTS_BLOCK_ID, 4);
unsigned AggregateAbbrev = 0;
@ -659,8 +659,8 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Char6));
CString6Abbrev = Stream.EmitAbbrev(Abbv);
}
}
SmallVector<uint64_t, 64> Record;
const ValueEnumerator::ValueList &Vals = VE.getValues();
@ -675,16 +675,16 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
CONSTANTS_SETTYPE_ABBREV);
Record.clear();
}
if (const InlineAsm *IA = dyn_cast<InlineAsm>(V)) {
Record.push_back(unsigned(IA->hasSideEffects()));
// Add the asm string.
const std::string &AsmStr = IA->getAsmString();
Record.push_back(AsmStr.size());
for (unsigned i = 0, e = AsmStr.size(); i != e; ++i)
Record.push_back(AsmStr[i]);
// Add the constraint string.
const std::string &ConstraintStr = IA->getConstraintString();
Record.push_back(ConstraintStr.size());
@ -711,11 +711,11 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
Code = bitc::CST_CODE_INTEGER;
AbbrevToUse = CONSTANTS_INTEGER_ABBREV;
} else { // Wide integers, > 64 bits in size.
// We have an arbitrary precision integer value to write whose
// bit width is > 64. However, in canonical unsigned integer
// We have an arbitrary precision integer value to write whose
// bit width is > 64. However, in canonical unsigned integer
// format it is likely that the high bits are going to be zero.
// So, we only write the number of active words.
unsigned NWords = IV->getValue().getActiveWords();
unsigned NWords = IV->getValue().getActiveWords();
const uint64_t *RawWords = IV->getValue().getRawData();
for (unsigned i = 0; i != NWords; ++i) {
int64_t V = RawWords[i];
@ -765,10 +765,10 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
unsigned char V = cast<ConstantInt>(C->getOperand(i))->getZExtValue();
Record.push_back(V);
isCStr7 &= (V & 128) == 0;
if (isCStrChar6)
if (isCStrChar6)
isCStrChar6 = BitCodeAbbrevOp::isChar6(V);
}
if (isCStrChar6)
AbbrevToUse = CString6Abbrev;
else if (isCStr7)
@ -863,7 +863,7 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal,
static void WriteModuleConstants(const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const ValueEnumerator::ValueList &Vals = VE.getValues();
// Find the first constant to emit, which is the first non-globalvalue value.
// We know globalvalues have been emitted by WriteModuleInfo.
for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
@ -883,7 +883,7 @@ static void WriteModuleConstants(const ValueEnumerator &VE,
/// instruction ID, then it is a forward reference, and it also includes the
/// type ID.
static bool PushValueAndType(const Value *V, unsigned InstID,
SmallVector<unsigned, 64> &Vals,
SmallVector<unsigned, 64> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
Vals.push_back(ValID);
@ -981,7 +981,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Vals.push_back(cast<CmpInst>(I).getPredicate());
break;
case Instruction::Ret:
case Instruction::Ret:
{
Code = bitc::FUNC_CODE_INST_RET;
unsigned NumOperands = I.getNumOperands();
@ -1019,13 +1019,13 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
const PointerType *PTy = cast<PointerType>(Callee->getType());
const FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
Code = bitc::FUNC_CODE_INST_INVOKE;
Vals.push_back(VE.getAttributeID(II->getAttributes()));
Vals.push_back(II->getCallingConv());
Vals.push_back(VE.getValueID(II->getNormalDest()));
Vals.push_back(VE.getValueID(II->getUnwindDest()));
PushValueAndType(Callee, InstID, Vals, VE);
// Emit value #'s for the fixed parameters.
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i+3))); // fixed param.
@ -1045,38 +1045,38 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Code = bitc::FUNC_CODE_INST_UNREACHABLE;
AbbrevToUse = FUNCTION_INST_UNREACHABLE_ABBREV;
break;
case Instruction::PHI:
Code = bitc::FUNC_CODE_INST_PHI;
Vals.push_back(VE.getTypeID(I.getType()));
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i)));
break;
case Instruction::Malloc:
Code = bitc::FUNC_CODE_INST_MALLOC;
Vals.push_back(VE.getTypeID(I.getType()));
Vals.push_back(VE.getValueID(I.getOperand(0))); // size.
Vals.push_back(Log2_32(cast<MallocInst>(I).getAlignment())+1);
break;
case Instruction::Free:
Code = bitc::FUNC_CODE_INST_FREE;
PushValueAndType(I.getOperand(0), InstID, Vals, VE);
break;
case Instruction::Alloca:
Code = bitc::FUNC_CODE_INST_ALLOCA;
Vals.push_back(VE.getTypeID(I.getType()));
Vals.push_back(VE.getValueID(I.getOperand(0))); // size.
Vals.push_back(Log2_32(cast<AllocaInst>(I).getAlignment())+1);
break;
case Instruction::Load:
Code = bitc::FUNC_CODE_INST_LOAD;
if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE)) // ptr
AbbrevToUse = FUNCTION_INST_LOAD_ABBREV;
Vals.push_back(Log2_32(cast<LoadInst>(I).getAlignment())+1);
Vals.push_back(cast<LoadInst>(I).isVolatile());
break;
@ -1092,16 +1092,16 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
const FunctionType *FTy = cast<FunctionType>(PTy->getElementType());
Code = bitc::FUNC_CODE_INST_CALL;
const CallInst *CI = cast<CallInst>(&I);
Vals.push_back(VE.getAttributeID(CI->getAttributes()));
Vals.push_back((CI->getCallingConv() << 1) | unsigned(CI->isTailCall()));
PushValueAndType(CI->getOperand(0), InstID, Vals, VE); // Callee
// Emit value #'s for the fixed parameters.
for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
Vals.push_back(VE.getValueID(I.getOperand(i+1))); // fixed param.
// Emit type/value pairs for varargs params.
if (FTy->isVarArg()) {
unsigned NumVarargs = I.getNumOperands()-1-FTy->getNumParams();
@ -1118,7 +1118,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
Vals.push_back(VE.getTypeID(I.getType())); // restype.
break;
}
Stream.EmitRecord(Code, Vals, AbbrevToUse);
Vals.clear();
}
@ -1133,27 +1133,27 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
// FIXME: Set up the abbrev, we know how many values there are!
// FIXME: We know if the type names can use 7-bit ascii.
SmallVector<unsigned, 64> NameVals;
for (ValueSymbolTable::const_iterator SI = VST.begin(), SE = VST.end();
SI != SE; ++SI) {
const ValueName &Name = *SI;
// Figure out the encoding to use for the name.
bool is7Bit = true;
bool isChar6 = true;
for (const char *C = Name.getKeyData(), *E = C+Name.getKeyLength();
C != E; ++C) {
if (isChar6)
if (isChar6)
isChar6 = BitCodeAbbrevOp::isChar6(*C);
if ((unsigned char)*C & 128) {
is7Bit = false;
break; // don't bother scanning the rest.
}
}
unsigned AbbrevToUse = VST_ENTRY_8_ABBREV;
// VST_ENTRY: [valueid, namechar x N]
// VST_BBENTRY: [bbid, namechar x N]
unsigned Code;
@ -1168,12 +1168,12 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
else if (is7Bit)
AbbrevToUse = VST_ENTRY_7_ABBREV;
}
NameVals.push_back(VE.getValueID(SI->getValue()));
for (const char *P = Name.getKeyData(),
*E = Name.getKeyData()+Name.getKeyLength(); P != E; ++P)
NameVals.push_back((unsigned char)*P);
// Emit the finished record.
Stream.EmitRecord(Code, NameVals, AbbrevToUse);
NameVals.clear();
@ -1182,27 +1182,27 @@ static void WriteValueSymbolTable(const ValueSymbolTable &VST,
}
/// WriteFunction - Emit a function body to the module stream.
static void WriteFunction(const Function &F, ValueEnumerator &VE,
static void WriteFunction(const Function &F, ValueEnumerator &VE,
BitstreamWriter &Stream) {
Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4);
VE.incorporateFunction(F);
SmallVector<unsigned, 64> Vals;
// Emit the number of basic blocks, so the reader can create them ahead of
// time.
Vals.push_back(VE.getBasicBlocks().size());
Stream.EmitRecord(bitc::FUNC_CODE_DECLAREBLOCKS, Vals);
Vals.clear();
// If there are function-local constants, emit them now.
unsigned CstStart, CstEnd;
VE.getFunctionConstantRange(CstStart, CstEnd);
WriteConstants(CstStart, CstEnd, VE, Stream, false);
// Keep a running idea of what the instruction ID is.
// Keep a running idea of what the instruction ID is.
unsigned InstID = CstEnd;
// Finally, emit all the instructions, in order.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
@ -1211,7 +1211,7 @@ static void WriteFunction(const Function &F, ValueEnumerator &VE,
if (I->getType() != Type::getVoidTy(F.getContext()))
++InstID;
}
// Emit names for all the instructions etc.
WriteValueSymbolTable(F.getValueSymbolTable(), VE, Stream);
@ -1225,9 +1225,9 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
const ValueEnumerator &VE,
BitstreamWriter &Stream) {
if (TST.empty()) return;
Stream.EnterSubblock(bitc::TYPE_SYMTAB_BLOCK_ID, 3);
// 7-bit fixed width VST_CODE_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::VST_CODE_ENTRY));
@ -1236,14 +1236,14 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 7));
unsigned V7Abbrev = Stream.EmitAbbrev(Abbv);
SmallVector<unsigned, 64> NameVals;
for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
TI != TE; ++TI) {
// TST_ENTRY: [typeid, namechar x N]
NameVals.push_back(VE.getTypeID(TI->second));
const std::string &Str = TI->first;
bool is7Bit = true;
for (unsigned i = 0, e = Str.size(); i != e; ++i) {
@ -1251,12 +1251,12 @@ static void WriteTypeSymbolTable(const TypeSymbolTable &TST,
if (Str[i] & 128)
is7Bit = false;
}
// Emit the finished record.
Stream.EmitRecord(bitc::VST_CODE_ENTRY, NameVals, is7Bit ? V7Abbrev : 0);
NameVals.clear();
}
Stream.ExitBlock();
}
@ -1266,18 +1266,18 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
// instances: CONSTANTS_BLOCK, FUNCTION_BLOCK and VALUE_SYMTAB_BLOCK. Other
// blocks can defined their abbrevs inline.
Stream.EnterBlockInfoBlock(2);
{ // 8-bit fixed-width VST_ENTRY/VST_BBENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 8));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array));
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 8));
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
if (Stream.EmitBlockInfoAbbrev(bitc::VALUE_SYMTAB_BLOCK_ID,
Abbv) != VST_ENTRY_8_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // 7-bit fixed width VST_ENTRY strings.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::VST_CODE_ENTRY));
@ -1308,9 +1308,9 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != VST_BBENTRY_6_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // SETTYPE abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_SETTYPE));
@ -1320,7 +1320,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_SETTYPE_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INTEGER abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_INTEGER));
@ -1329,7 +1329,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_INTEGER_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // CE_CAST abbrev for CONSTANTS_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::CST_CODE_CE_CAST));
@ -1349,9 +1349,9 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != CONSTANTS_NULL_Abbrev)
llvm_unreachable("Unexpected abbrev ordering!");
}
// FIXME: This should only use space for first class types!
{ // INST_LOAD abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_LOAD));
@ -1394,7 +1394,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != FUNCTION_INST_CAST_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
{ // INST_RET abbrev for FUNCTION_BLOCK.
BitCodeAbbrev *Abbv = new BitCodeAbbrev();
Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_RET));
@ -1417,7 +1417,7 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
Abbv) != FUNCTION_INST_UNREACHABLE_ABBREV)
llvm_unreachable("Unexpected abbrev ordering!");
}
Stream.ExitBlock();
}
@ -1425,26 +1425,26 @@ static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
/// WriteModule - Emit the specified module to the bitstream.
static void WriteModule(const Module *M, BitstreamWriter &Stream) {
Stream.EnterSubblock(bitc::MODULE_BLOCK_ID, 3);
// Emit the version number if it is non-zero.
if (CurVersion) {
SmallVector<unsigned, 1> Vals;
Vals.push_back(CurVersion);
Stream.EmitRecord(bitc::MODULE_CODE_VERSION, Vals);
}
// Analyze the module, enumerating globals, functions, etc.
ValueEnumerator VE(M);
// Emit blockinfo, which defines the standard abbreviations etc.
WriteBlockInfo(VE, Stream);
// Emit information about parameter attributes.
WriteAttributeTable(VE, Stream);
// Emit information describing all of the types in the module.
WriteTypeTable(VE, Stream);
// Emit top-level description of module, including target triple, inline asm,
// descriptors for global variables, and function prototype info.
WriteModuleInfo(M, VE, Stream);
@ -1462,13 +1462,13 @@ static void WriteModule(const Module *M, BitstreamWriter &Stream) {
// Emit metadata.
WriteModuleMetadataStore(M, VE, Stream);
// Emit the type symbol table information.
WriteTypeSymbolTable(M->getTypeSymbolTable(), VE, Stream);
// Emit names for globals/functions etc.
WriteValueSymbolTable(M->getValueSymbolTable(), VE, Stream);
Stream.ExitBlock();
}
@ -1476,7 +1476,7 @@ static void WriteModule(const Module *M, BitstreamWriter &Stream) {
/// header and trailer to make it compatible with the system archiver. To do
/// this we emit the following header, and then emit a trailer that pads the
/// file out to be a multiple of 16 bytes.
///
///
/// struct bc_header {
/// uint32_t Magic; // 0x0B17C0DE
/// uint32_t Version; // Version, currently always 0.
@ -1493,7 +1493,7 @@ enum {
static void EmitDarwinBCHeader(BitstreamWriter &Stream,
const std::string &TT) {
unsigned CPUType = ~0U;
// Match x86_64-*, i[3-9]86-*, powerpc-*, powerpc64-*. The CPUType is a
// magic number from /usr/include/mach/machine.h. It is ok to reproduce the
// specific constants here because they are implicitly part of the Darwin ABI.
@ -1502,7 +1502,7 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
DARWIN_CPU_TYPE_X86 = 7,
DARWIN_CPU_TYPE_POWERPC = 18
};
if (TT.find("x86_64-") == 0)
CPUType = DARWIN_CPU_TYPE_X86 | DARWIN_CPU_ARCH_ABI64;
else if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
@ -1512,10 +1512,10 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
CPUType = DARWIN_CPU_TYPE_POWERPC;
else if (TT.find("powerpc64-") == 0)
CPUType = DARWIN_CPU_TYPE_POWERPC | DARWIN_CPU_ARCH_ABI64;
// Traditional Bitcode starts after header.
unsigned BCOffset = DarwinBCHeaderSize;
Stream.Emit(0x0B17C0DE, 32);
Stream.Emit(0 , 32); // Version.
Stream.Emit(BCOffset , 32);
@ -1528,7 +1528,7 @@ static void EmitDarwinBCHeader(BitstreamWriter &Stream,
static void EmitDarwinBCTrailer(BitstreamWriter &Stream, unsigned BufferSize) {
// Update the size field in the header.
Stream.BackpatchWord(DarwinBCSizeFieldOffset, BufferSize-DarwinBCHeaderSize);
// If the file is not a multiple of 16 bytes, insert dummy padding.
while (BufferSize & 15) {
Stream.Emit(0, 8);
@ -1542,18 +1542,18 @@ static void EmitDarwinBCTrailer(BitstreamWriter &Stream, unsigned BufferSize) {
void llvm::WriteBitcodeToFile(const Module *M, raw_ostream &Out) {
std::vector<unsigned char> Buffer;
BitstreamWriter Stream(Buffer);
Buffer.reserve(256*1024);
WriteBitcodeToStream( M, Stream );
// If writing to stdout, set binary mode.
if (&llvm::outs() == &Out)
sys::Program::ChangeStdoutToBinary();
// Write the generated bitstream to "Out".
Out.write((char*)&Buffer.front(), Buffer.size());
// Make sure it hits disk now.
Out.flush();
}
@ -1565,7 +1565,7 @@ void llvm::WriteBitcodeToStream(const Module *M, BitstreamWriter &Stream) {
bool isDarwin = M->getTargetTriple().find("-darwin") != std::string::npos;
if (isDarwin)
EmitDarwinBCHeader(Stream, M->getTargetTriple());
// Emit the file header.
Stream.Emit((unsigned)'B', 8);
Stream.Emit((unsigned)'C', 8);

79
lib/Bitcode/Writer/ValueEnumerator.cpp
View File

@ -57,10 +57,10 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
I != E; ++I)
EnumerateValue(I);
// Remember what is the cutoff between globalvalue's and other constants.
unsigned FirstConstant = Values.size();
// Enumerate the global variable initializers.
for (Module::const_global_iterator I = M->global_begin(),
E = M->global_end(); I != E; ++I)
@ -71,25 +71,25 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
I != E; ++I)
EnumerateValue(I->getAliasee());
// Enumerate types used by the type symbol table.
EnumerateTypeSymbolTable(M->getTypeSymbolTable());
// Insert constants that are named at module level into the slot pool so that
// the module symbol table can refer to them...
EnumerateValueSymbolTable(M->getValueSymbolTable());
// Enumerate types used by function bodies and argument lists.
for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) {
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
I != E; ++I)
EnumerateType(I->getType());
Metadata &TheMetadata = F->getContext().getMetadata();
Metadata &TheMetadata = F->getContext().getMetadata();
for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E;++I){
for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
OI != E; ++OI)
EnumerateOperandType(*OI);
EnumerateType(I->getType());
@ -98,23 +98,23 @@ ValueEnumerator::ValueEnumerator(const Module *M) {
else if (const InvokeInst *II = dyn_cast<InvokeInst>(I))
EnumerateAttributes(II->getAttributes());
// Enumerate metadata attached with this instruction.
const Metadata::MDMapTy *MDs = TheMetadata.getMDs(I);
if (MDs)
for (Metadata::MDMapTy::const_iterator MI = MDs->begin(),
ME = MDs->end(); MI != ME; ++MI)
if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
EnumerateMetadata(MDN);
// Enumerate metadata attached with this instruction.
const Metadata::MDMapTy *MDs = TheMetadata.getMDs(I);
if (MDs)
for (Metadata::MDMapTy::const_iterator MI = MDs->begin(),
ME = MDs->end(); MI != ME; ++MI)
if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
EnumerateMetadata(MDN);
}
}
// Optimize constant ordering.
OptimizeConstants(FirstConstant, Values.size());
// Sort the type table by frequency so that most commonly used types are early
// in the table (have low bit-width).
std::stable_sort(Types.begin(), Types.end(), CompareByFrequency);
// Partition the Type ID's so that the single-value types occur before the
// aggregate types. This allows the aggregate types to be dropped from the
// type table after parsing the global variable initializers.
@ -129,7 +129,7 @@ unsigned ValueEnumerator::getInstructionID(const Instruction *Inst) const {
InstructionMapType::const_iterator I = InstructionMap.find(Inst);
assert (I != InstructionMap.end() && "Instruction is not mapped!");
return I->second;
}
}
void ValueEnumerator::setInstructionID(const Instruction *I) {
InstructionMap[I] = InstructionCount++;
@ -141,12 +141,12 @@ unsigned ValueEnumerator::getValueID(const Value *V) const {
assert(I != MDValueMap.end() && "Value not in slotcalculator!");
return I->second-1;
}
ValueMapType::const_iterator I = ValueMap.find(V);
assert(I != ValueMap.end() && "Value not in slotcalculator!");
return I->second-1;
}
// Optimize constant ordering.
namespace {
struct CstSortPredicate {
@ -156,7 +156,7 @@ namespace {
const std::pair<const Value*, unsigned> &RHS) {
// Sort by plane.
if (LHS.first->getType() != RHS.first->getType())
return VE.getTypeID(LHS.first->getType()) <
return VE.getTypeID(LHS.first->getType()) <
VE.getTypeID(RHS.first->getType());
// Then by frequency.
return LHS.second > RHS.second;
@ -167,15 +167,15 @@ namespace {
/// OptimizeConstants - Reorder constant pool for denser encoding.
void ValueEnumerator::OptimizeConstants(unsigned CstStart, unsigned CstEnd) {
if (CstStart == CstEnd || CstStart+1 == CstEnd) return;
CstSortPredicate P(*this);
std::stable_sort(Values.begin()+CstStart, Values.begin()+CstEnd, P);
// Ensure that integer constants are at the start of the constant pool. This
// is important so that GEP structure indices come before gep constant exprs.
std::partition(Values.begin()+CstStart, Values.begin()+CstEnd,
isIntegerValue);
// Rebuild the modified portion of ValueMap.
for (; CstStart != CstEnd; ++CstStart)
ValueMap[Values[CstStart].first] = CstStart+1;
@ -185,7 +185,7 @@ void ValueEnumerator::OptimizeConstants(unsigned CstStart, unsigned CstEnd) {
/// EnumerateTypeSymbolTable - Insert all of the types in the specified symbol
/// table.
void ValueEnumerator::EnumerateTypeSymbolTable(const TypeSymbolTable &TST) {
for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
for (TypeSymbolTable::const_iterator TI = TST.begin(), TE = TST.end();
TI != TE; ++TI)
EnumerateType(TI->second);
}
@ -193,7 +193,7 @@ void ValueEnumerator::EnumerateTypeSymbolTable(const TypeSymbolTable &TST) {
/// EnumerateValueSymbolTable - Insert all of the values in the specified symbol
/// table into the values table.
void ValueEnumerator::EnumerateValueSymbolTable(const ValueSymbolTable &VST) {
for (ValueSymbolTable::const_iterator VI = VST.begin(), VE = VST.end();
for (ValueSymbolTable::const_iterator VI = VST.begin(), VE = VST.end();
VI != VE; ++VI)
EnumerateValue(VI->getValue());
}
@ -254,7 +254,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
// Enumerate the type of this value.
EnumerateType(V->getType());
if (const Constant *C = dyn_cast<Constant>(V)) {
if (isa<GlobalValue>(C)) {
// Initializers for globals are handled explicitly elsewhere.
@ -266,7 +266,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
// If a constant has operands, enumerate them. This makes sure that if a
// constant has uses (for example an array of const ints), that they are
// inserted also.
// We prefer to enumerate them with values before we enumerate the user
// itself. This makes it more likely that we can avoid forward references
// in the reader. We know that there can be no cycles in the constants
@ -274,7 +274,7 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
for (User::const_op_iterator I = C->op_begin(), E = C->op_end();
I != E; ++I)
EnumerateValue(*I);
// Finally, add the value. Doing this could make the ValueID reference be
// dangling, don't reuse it.
Values.push_back(std::make_pair(V, 1U));
@ -291,17 +291,17 @@ void ValueEnumerator::EnumerateValue(const Value *V) {
void ValueEnumerator::EnumerateType(const Type *Ty) {
unsigned &TypeID = TypeMap[Ty];
if (TypeID) {
// If we've already seen this type, just increase its occurrence count.
Types[TypeID-1].second++;
return;
}
// First time we saw this type, add it.
Types.push_back(std::make_pair(Ty, 1U));
TypeID = Types.size();
// Enumerate subtypes.
for (Type::subtype_iterator I = Ty->subtype_begin(), E = Ty->subtype_end();
I != E; ++I)
@ -347,18 +347,18 @@ void ValueEnumerator::EnumerateAttributes(const AttrListPtr &PAL) {
void ValueEnumerator::incorporateFunction(const Function &F) {
NumModuleValues = Values.size();
// Adding function arguments to the value table.
for(Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I)
EnumerateValue(I);
FirstFuncConstantID = Values.size();
// Add all function-level constants to the value table.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
OI != E; ++OI) {
if ((isa<Constant>(*OI) && !isa<GlobalValue>(*OI)) ||
isa<InlineAsm>(*OI))
@ -367,16 +367,16 @@ void ValueEnumerator::incorporateFunction(const Function &F) {
BasicBlocks.push_back(BB);
ValueMap[BB] = BasicBlocks.size();
}
// Optimize the constant layout.
OptimizeConstants(FirstFuncConstantID, Values.size());
// Add the function's parameter attributes so they are available for use in
// the function's instruction.
EnumerateAttributes(F.getAttributes());
FirstInstID = Values.size();
// Add all of the instructions.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I) {
@ -392,8 +392,7 @@ void ValueEnumerator::purgeFunction() {
ValueMap.erase(Values[i].first);
for (unsigned i = 0, e = BasicBlocks.size(); i != e; ++i)
ValueMap.erase(BasicBlocks[i]);
Values.resize(NumModuleValues);
BasicBlocks.clear();
}

4
lib/CodeGen/DwarfEHPrepare.cpp
View File

@ -134,7 +134,7 @@ bool DwarfEHPrepare::NormalizeLandingPads() {
break;
}
}
if (OnlyUnwoundTo) {
// Only unwind edges lead to the landing pad. Remember the landing pad.
LandingPads.insert(LPad);
@ -254,7 +254,7 @@ bool DwarfEHPrepare::LowerUnwinds() {
// Create the call...
CallInst *CI = CallInst::Create(RewindFunction,
CreateReadOfExceptionValue(TI->getParent()),
CreateReadOfExceptionValue(TI->getParent()),
"", TI);
CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
// ...followed by an UnreachableInst.

6
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -74,7 +74,7 @@ namespace {
public:
static char ID;
/// Construct a PBQP register allocator.
PBQPRegAlloc() : MachineFunctionPass(&ID) {}
@ -696,7 +696,7 @@ bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
// Clear the existing allocation.
vrm->clearAllVirt();
// Iterate over the nodes mapping the PBQP solution to a register assignment.
for (unsigned node = 0; node < node2LI.size(); ++node) {
unsigned virtReg = node2LI[node]->reg,
@ -764,7 +764,7 @@ void PBQPRegAlloc::finalizeAlloc() const {
// First allocate registers for the empty intervals.
for (LiveIntervalSet::const_iterator
itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
itr != end; ++itr) {
LiveInterval *li = *itr;

140
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -162,7 +162,7 @@ MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
"TargetLowering::EmitInstrWithCustomInserter!";
#endif
llvm_unreachable(0);
return 0;
return 0;
}
/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
@ -225,7 +225,7 @@ static void EmitLiveInCopy(MachineBasicBlock *MBB,
bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
if (Coalesced) {
if (&*InsertPos == UseMI) ++InsertPos;
@ -379,13 +379,13 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
// as a tail call, cease emitting nodes for this block.
for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I) {
if (MDDbgKind) {
// Update DebugLoc if debug information is attached with this
// Update DebugLoc if debug information is attached with this
// instruction.
if (MDNode *Dbg =
dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, I))) {
DILocation DILoc(Dbg);
DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
SDL->setCurDebugLoc(Loc);
if (MDNode *Dbg =
dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, I))) {
DILocation DILoc(Dbg);
DebugLoc Loc = ExtractDebugLocation(DILoc, MF->getDebugLocInfo());
SDL->setCurDebugLoc(Loc);
}
}
if (!isa<TerminatorInst>(I))
@ -407,7 +407,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
SDL->visit(*LLVMBB->getTerminator());
}
}
// Make sure the root of the DAG is up-to-date.
CurDAG->setRoot(SDL->getControlRoot());
@ -419,44 +419,44 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode*, 128> VisitedNodes;
SmallVector<SDNode*, 128> Worklist;
Worklist.push_back(CurDAG->getRoot().getNode());
APInt Mask;
APInt KnownZero;
APInt KnownOne;
while (!Worklist.empty()) {
SDNode *N = Worklist.back();
Worklist.pop_back();
// If we've already seen this node, ignore it.
if (!VisitedNodes.insert(N))
continue;
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
if (N->getOperand(i).getValueType() == MVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
// If this is a CopyToReg with a vreg dest, process it.
if (N->getOpcode() != ISD::CopyToReg)
continue;
unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
if (!TargetRegisterInfo::isVirtualRegister(DestReg))
continue;
// Ignore non-scalar or non-integer values.
SDValue Src = N->getOperand(2);
EVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
// Only install this information if it tells us something.
if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
DestReg -= TargetRegisterInfo::FirstVirtualRegister;
@ -494,10 +494,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Combine(Unrestricted, *AA, OptLevel);
}
DEBUG(errs() << "Optimized lowered selection DAG:\n");
DEBUG(CurDAG->dump());
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
if (!DisableLegalizeTypes) {
@ -561,7 +561,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(CurDAG->dump());
}
}
if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
if (TimePassesIsEnabled) {
@ -570,10 +570,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Legalize(DisableLegalizeTypes, OptLevel);
}
DEBUG(errs() << "Legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
// Run the DAG combiner in post-legalize mode.
@ -583,12 +583,12 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
} else {
CurDAG->Combine(NoIllegalOperations, *AA, OptLevel);
}
DEBUG(errs() << "Optimized legalized selection DAG:\n");
DEBUG(CurDAG->dump());
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
@ -617,7 +617,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
if (ViewSUnitDAGs) Scheduler->viewGraph();
// Emit machine code to BB. This can change 'BB' to the last block being
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Creation", GroupName);
@ -636,7 +636,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(errs() << "Selected machine code:\n");
DEBUG(BB->dump());
}
}
void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
MachineFunction &MF,
@ -740,17 +740,17 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
FastIS->startNewBlock(BB);
// Do FastISel on as many instructions as possible.
for (; BI != End; ++BI) {
if (MDDbgKind) {
// Update DebugLoc if debug information is attached with this
// instruction.
if (MDNode *Dbg =
dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, BI))) {
DILocation DILoc(Dbg);
DebugLoc Loc = ExtractDebugLocation(DILoc,
MF.getDebugLocInfo());
FastIS->setCurDebugLoc(Loc);
}
}
if (MDDbgKind) {
// Update DebugLoc if debug information is attached with this
// instruction.
if (MDNode *Dbg =
dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, BI))) {
DILocation DILoc(Dbg);
DebugLoc Loc = ExtractDebugLocation(DILoc,
MF.getDebugLocInfo());
FastIS->setCurDebugLoc(Loc);
}
}
// Just before the terminator instruction, insert instructions to
// feed PHI nodes in successor blocks.
@ -760,7 +760,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
errs() << "FastISel miss: ";
BI->dump();
}
assert(!EnableFastISelAbort &&
assert(!EnableFastISelAbort &&
"FastISel didn't handle a PHI in a successor");
break;
}
@ -838,7 +838,7 @@ SelectionDAGISel::FinishBasicBlock() {
errs() << "Node " << i << " : ("
<< SDL->PHINodesToUpdate[i].first
<< ", " << SDL->PHINodesToUpdate[i].second << ")\n");
// Next, now that we know what the last MBB the LLVM BB expanded is, update
// PHI nodes in successors.
if (SDL->SwitchCases.empty() &&
@ -867,7 +867,7 @@ SelectionDAGISel::FinishBasicBlock() {
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
}
}
for (unsigned j = 0, ej = SDL->BitTestCases[i].Cases.size(); j != ej; ++j) {
// Set the current basic block to the mbb we wish to insert the code into
@ -882,8 +882,8 @@ SelectionDAGISel::FinishBasicBlock() {
SDL->visitBitTestCase(SDL->BitTestCases[i].Default,
SDL->BitTestCases[i].Reg,
SDL->BitTestCases[i].Cases[j]);
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
@ -936,7 +936,7 @@ SelectionDAGISel::FinishBasicBlock() {
CodeGenAndEmitDAG();
SDL->clear();
}
// Set the current basic block to the mbb we wish to insert the code into
BB = SDL->JTCases[i].second.MBB;
SDL->setCurrentBasicBlock(BB);
@ -945,7 +945,7 @@ SelectionDAGISel::FinishBasicBlock() {
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
SDL->clear();
// Update PHI Nodes
for (unsigned pi = 0, pe = SDL->PHINodesToUpdate.size(); pi != pe; ++pi) {
MachineInstr *PHI = SDL->PHINodesToUpdate[pi].first;
@ -968,7 +968,7 @@ SelectionDAGISel::FinishBasicBlock() {
}
}
SDL->JTCases.clear();
// If the switch block involved a branch to one of the actual successors, we
// need to update PHI nodes in that block.
for (unsigned i = 0, e = SDL->PHINodesToUpdate.size(); i != e; ++i) {
@ -981,19 +981,19 @@ SelectionDAGISel::FinishBasicBlock() {
PHI->addOperand(MachineOperand::CreateMBB(BB));
}
}
// If we generated any switch lowering information, build and codegen any
// additional DAGs necessary.
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
// Set the current basic block to the mbb we wish to insert the code into
MachineBasicBlock *ThisBB = BB = SDL->SwitchCases[i].ThisBB;
SDL->setCurrentBasicBlock(BB);
// Emit the code
SDL->visitSwitchCase(SDL->SwitchCases[i]);
CurDAG->setRoot(SDL->getRoot());
CodeGenAndEmitDAG();
// Handle any PHI nodes in successors of this chunk, as if we were coming
// from the original BB before switch expansion. Note that PHI nodes can
// occur multiple times in PHINodesToUpdate. We have to be very careful to
@ -1020,11 +1020,11 @@ SelectionDAGISel::FinishBasicBlock() {
}
}
}
// Don't process RHS if same block as LHS.
if (BB == SDL->SwitchCases[i].FalseBB)
SDL->SwitchCases[i].FalseBB = 0;
// If we haven't handled the RHS, do so now. Otherwise, we're done.
SDL->SwitchCases[i].TrueBB = SDL->SwitchCases[i].FalseBB;
SDL->SwitchCases[i].FalseBB = 0;
@ -1044,12 +1044,12 @@ SelectionDAGISel::FinishBasicBlock() {
///
ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
if (!Ctor) {
Ctor = ISHeuristic;
RegisterScheduler::setDefault(Ctor);
}
return Ctor(this, OptLevel);
}
@ -1066,25 +1066,25 @@ ScheduleHazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
return true;
// TODO: check to see if missing bits are just not demanded.
// Otherwise, this pattern doesn't match.
@ -1095,32 +1095,32 @@ bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
/// the dag combiner simplified the 255, we still want to match. RHS is the
/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
/// specified in the .td file (e.g. 255).
bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
int64_t DesiredMaskS) const {
const APInt &ActualMask = RHS->getAPIntValue();
const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
// If the actual mask exactly matches, success!
if (ActualMask == DesiredMask)
return true;
// If the actual AND mask is allowing unallowed bits, this doesn't match.
if (ActualMask.intersects(~DesiredMask))
return false;
// Otherwise, the DAG Combiner may have proven that the value coming in is
// either already zero or is not demanded. Check for known zero input bits.
APInt NeededMask = DesiredMask & ~ActualMask;
APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
// If all the missing bits in the or are already known to be set, match!
if ((NeededMask & KnownOne) == NeededMask)
return true;
// TODO: check to see if missing bits are just not demanded.
// Otherwise, this pattern doesn't match.
return false;
}
@ -1139,7 +1139,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
unsigned i = 2, e = InOps.size();
if (InOps[e-1].getValueType() == MVT::Flag)
--e; // Don't process a flag operand if it is here.
while (i != e) {
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
if ((Flags & 7) != 4 /*MEM*/) {
@ -1156,7 +1156,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
llvm_report_error("Could not match memory address. Inline asm"
" failure!");
}
// Add this to the output node.
EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
@ -1165,7 +1165,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
i += 2;
}
}
// Add the flag input back if present.
if (e != InOps.size())
Ops.push_back(InOps.back());

134
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -62,7 +62,7 @@ PhysJoinTweak("tweak-phys-join-heuristics",
cl::desc("Tweak heuristics for joining phys reg with vr"),
cl::init(false), cl::Hidden);
static RegisterPass<SimpleRegisterCoalescing>
static RegisterPass<SimpleRegisterCoalescing>
X("simple-register-coalescing", "Simple Register Coalescing");
// Declare that we implement the RegisterCoalescer interface
@ -110,13 +110,13 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
// Get the location that B is defined at. Two options: either this value has
// an unknown definition point or it is defined at CopyIdx. If unknown, we
// an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
// AValNo is the value number in A that defines the copy, A3 in the example.
MachineInstrIndex CopyUseIdx = li_->getUseIndex(CopyIdx);
LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
@ -142,28 +142,28 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
// The coalescer has no idea there was a def in the middle of [174,230].
if (AValNo->hasRedefByEC())
return false;
// If AValNo is defined as a copy from IntB, we can potentially process this.
// If AValNo is defined as a copy from IntB, we can potentially process this.
// Get the instruction that defines this value number.
unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
if (!SrcReg) return false; // Not defined by a copy.
// If the value number is not defined by a copy instruction, ignore it.
// If the source register comes from an interval other than IntB, we can't
// handle this.
if (SrcReg != IntB.reg) return false;
// Get the LiveRange in IntB that this value number starts with.
LiveInterval::iterator ValLR =
IntB.FindLiveRangeContaining(li_->getPrevSlot(AValNo->def));
assert(ValLR != IntB.end() && "Live range not found!");
// Make sure that the end of the live range is inside the same block as
// CopyMI.
MachineInstr *ValLREndInst =
li_->getInstructionFromIndex(li_->getPrevSlot(ValLR->end));
if (!ValLREndInst ||
if (!ValLREndInst ||
ValLREndInst->getParent() != CopyMI->getParent()) return false;
// Okay, we now know that ValLR ends in the same block that the CopyMI
@ -185,26 +185,26 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
return false;
}
}
DEBUG({
errs() << "\nExtending: ";
IntB.print(errs(), tri_);
});
MachineInstrIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction
// that defines this value #'. Update the the valnum with the new defining
// instruction #.
BValNo->def = FillerStart;
BValNo->setCopy(0);
// Okay, we can merge them. We need to insert a new liverange:
// [ValLR.end, BLR.begin) of either value number, then we merge the
// two value numbers.
IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
// If the IntB live range is assigned to a physical register, and if that
// physreg has sub-registers, update their live intervals as well.
// physreg has sub-registers, update their live intervals as well.
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
@ -309,13 +309,13 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
assert(BLR != IntB.end() && "Live range not found!");
VNInfo *BValNo = BLR->valno;
// Get the location that B is defined at. Two options: either this value has
// an unknown definition point or it is defined at CopyIdx. If unknown, we
// an unknown definition point or it is defined at CopyIdx. If unknown, we
// can't process it.
if (!BValNo->getCopy()) return false;
assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
// AValNo is the value number in A that defines the copy, A3 in the example.
LiveInterval::iterator ALR =
IntA.FindLiveRangeContaining(li_->getPrevSlot(CopyIdx));
@ -491,7 +491,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
IntB.addRange(LiveRange(AI->start, End, ValNo));
// If the IntB live range is assigned to a physical register, and if that
// physreg has sub-registers, update their live intervals as well.
// physreg has sub-registers, update their live intervals as well.
if (BHasSubRegs) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
LiveInterval &SRLI = li_->getInterval(*SR);
@ -832,11 +832,11 @@ void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
// at the same point: %reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
//
// bb5:
// 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
// 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
// 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
// 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
// 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
// 60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
// 68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
// 76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
// 84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
// 96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
//
// Do not remove the kill marker on t2LDRi12.
UseMO.setIsKill(false);
@ -1309,7 +1309,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
DEBUG(errs() << "\tCopy already coalesced.\n");
return false; // Not coalescable.
}
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
@ -1318,7 +1318,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
DEBUG(errs() << "\tCan not coalesce physregs.\n");
return false; // Not coalescable.
}
// We only join virtual registers with allocatable physical registers.
if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
DEBUG(errs() << "\tSrc reg is unallocatable physreg.\n");
@ -1543,7 +1543,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
return false;
if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
return false;
LiveInterval &SrcInt = li_->getInterval(SrcReg);
LiveInterval &DstInt = li_->getInterval(DstReg);
assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
@ -1643,7 +1643,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
return true;
// If we can eliminate the copy without merging the live ranges, do so now.
if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
(AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
@ -1651,7 +1651,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
JoinedCopies.insert(CopyMI);
return true;
}
// Otherwise, we are unable to join the intervals.
DEBUG(errs() << "Interference!\n");
Again = true; // May be possible to coalesce later.
@ -1666,7 +1666,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
}
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
"LiveInterval::join didn't work right!");
// If we're about to merge live ranges into a physical register live interval,
// we have to update any aliased register's live ranges to indicate that they
// have clobbered values for this range.
@ -1687,7 +1687,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
RealInt.addKills(NewValNo, ValNo->kills);
RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
}
RealInt.weight += SavedLI->weight;
RealInt.weight += SavedLI->weight;
DstReg = RealDstReg ? RealDstReg : RealSrcReg;
}
@ -1806,7 +1806,7 @@ static unsigned ComputeUltimateVN(VNInfo *VNI,
// been computed, return it.
if (OtherValNoAssignments[OtherValNo->id] >= 0)
return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
// Mark this value number as currently being computed, then ask what the
// ultimate value # of the other value is.
ThisValNoAssignments[VN] = -2;
@ -1856,16 +1856,16 @@ bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
/// joins them and returns true.
bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
assert(RHS.containsOneValue());
// Some number (potentially more than one) value numbers in the current
// interval may be defined as copies from the RHS. Scan the overlapping
// portions of the LHS and RHS, keeping track of this and looking for
// overlapping live ranges that are NOT defined as copies. If these exist, we
// cannot coalesce.
LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
if (LHSIt->start < RHSIt->start) {
LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
if (LHSIt != LHS.begin()) --LHSIt;
@ -1873,9 +1873,9 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
if (RHSIt != RHS.begin()) --RHSIt;
}
SmallVector<VNInfo*, 8> EliminatedLHSVals;
while (1) {
// Determine if these live intervals overlap.
bool Overlaps = false;
@ -1883,7 +1883,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
Overlaps = LHSIt->end > RHSIt->start;
else
Overlaps = RHSIt->end > LHSIt->start;
// If the live intervals overlap, there are two interesting cases: if the
// LHS interval is defined by a copy from the RHS, it's ok and we record
// that the LHS value # is the same as the RHS. If it's not, then we cannot
@ -1901,7 +1901,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
// vr1025 = copy vr1024
// ..
// BB2:
// vr1024 = op
// vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesce them since the live range of vr1025 intersects the
@ -1910,12 +1910,12 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
return false;
EliminatedLHSVals.push_back(LHSIt->valno);
}
// We know this entire LHS live range is okay, so skip it now.
if (++LHSIt == LHSEnd) break;
continue;
}
if (LHSIt->end < RHSIt->end) {
if (++LHSIt == LHSEnd) break;
} else {
@ -1939,7 +1939,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
// vr1025 = copy vr1024
// ..
// BB2:
// vr1024 = op
// vr1024 = op
// = vr1025
// Even though vr1025 is copied from vr1024, it's not safe to
// coalesced them since live range of vr1025 intersects the
@ -1953,11 +1953,11 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
}
}
}
if (++RHSIt == RHSEnd) break;
}
}
// If we got here, we know that the coalescing will be successful and that
// the value numbers in EliminatedLHSVals will all be merged together. Since
// the most common case is that EliminatedLHSVals has a single number, we
@ -1989,14 +1989,14 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
} else {
LHSValNo = EliminatedLHSVals[0];
}
// Okay, now that there is a single LHS value number that we're merging the
// RHS into, update the value number info for the LHS to indicate that the
// value number is defined where the RHS value number was.
const VNInfo *VNI = RHS.getValNumInfo(0);
LHSValNo->def = VNI->def;
LHSValNo->setCopy(VNI->getCopy());
// Okay, the final step is to loop over the RHS live intervals, adding them to
// the LHS.
if (VNI->hasPHIKill())
@ -2007,7 +2007,7 @@ bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
LHS.ComputeJoinedWeight(RHS);
// Update regalloc hint if both are virtual registers.
if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
@ -2094,13 +2094,13 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
}
}
}
// Compute ultimate value numbers for the LHS and RHS values.
if (RHS.containsOneValue()) {
// Copies from a liveinterval with a single value are simple to handle and
// very common, handle the special case here. This is important, because
// often RHS is small and LHS is large (e.g. a physreg).
// Find out if the RHS is defined as a copy from some value in the LHS.
int RHSVal0DefinedFromLHS = -1;
int RHSValID = -1;
@ -2123,11 +2123,11 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
RHSValID = RHSValNoInfo->id;
RHSVal0DefinedFromLHS = RHSValID;
}
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.resize(LHS.getNumValNums(), NULL);
// Okay, *all* of the values in LHS that are defined as a copy from RHS
// should now get updated.
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
@ -2159,7 +2159,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
LHSValNoAssignments[VN] = VN;
}
}
assert(RHSValID != -1 && "Didn't find value #?");
RHSValNoAssignments[0] = RHSValID;
if (RHSVal0DefinedFromLHS != -1) {
@ -2175,17 +2175,17 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
VNInfo *VNI = *i;
if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
// DstReg is known to be a register in the LHS interval. If the src is
// from the RHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
continue;
// Figure out the value # from the RHS.
LHSValsDefinedFromRHS[VNI]=
RHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
// Loop over the value numbers of the RHS, seeing if any are defined from
// the LHS.
for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
@ -2193,26 +2193,26 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
VNInfo *VNI = *i;
if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
continue;
// DstReg is known to be a register in the RHS interval. If the src is
// from the LHS interval, we can use its value #.
if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
continue;
// Figure out the value # from the LHS.
RHSValsDefinedFromLHS[VNI]=
LHS.getLiveRangeContaining(li_->getPrevSlot(VNI->def))->valno;
}
LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
i != e; ++i) {
VNInfo *VNI = *i;
unsigned VN = VNI->id;
if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
continue;
ComputeUltimateVN(VNI, NewVNInfo,
LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
@ -2230,20 +2230,20 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
RHSValNoAssignments[VN] = NewVNInfo.size()-1;
continue;
}
ComputeUltimateVN(VNI, NewVNInfo,
RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
RHSValNoAssignments, LHSValNoAssignments);
}
}
// Armed with the mappings of LHS/RHS values to ultimate values, walk the
// interval lists to see if these intervals are coalescable.
LiveInterval::const_iterator I = LHS.begin();
LiveInterval::const_iterator IE = LHS.end();
LiveInterval::const_iterator J = RHS.begin();
LiveInterval::const_iterator JE = RHS.end();
// Skip ahead until the first place of potential sharing.
if (I->start < J->start) {
I = std::upper_bound(I, IE, J->start);
@ -2252,7 +2252,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
J = std::upper_bound(J, JE, I->start);
if (J != RHS.begin()) --J;
}
while (1) {
// Determine if these two live ranges overlap.
bool Overlaps;
@ -2270,7 +2270,7 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
RHSValNoAssignments[J->valno->id])
return false;
}
if (I->end < J->end) {
++I;
if (I == IE) break;
@ -2341,7 +2341,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) {
MachineInstr *Inst = MII++;
// If this isn't a copy nor a extract_subreg, we can't join intervals.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
@ -2419,7 +2419,7 @@ void SimpleRegisterCoalescing::joinIntervals() {
for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
}
// Joining intervals can allow other intervals to be joined. Iteratively join
// until we make no progress.
bool ProgressMade = true;
@ -2706,7 +2706,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
if (Hint.first || Hint.second)
LI.weight *= 1.01F;
// Divide the weight of the interval by its size. This encourages
// Divide the weight of the interval by its size. This encourages
// spilling of intervals that are large and have few uses, and
// discourages spilling of small intervals with many uses.
LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;

2
lib/Support/APInt.cpp
View File

@ -2054,7 +2054,7 @@ void APInt::fromString(unsigned numbits, const StringRef& str, uint8_t radix) {
assert(((slen-1)*3 <= numbits || radix != 8) && "Insufficient bit width");
assert(((slen-1)*4 <= numbits || radix != 16) && "Insufficient bit width");
assert((((slen-1)*64)/22 <= numbits || radix != 10)
&& "Insufficient bit width");
&& "Insufficient bit width");
// Allocate memory
if (!isSingleWord())

4
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -31,7 +31,7 @@
using namespace llvm;
namespace {
class AlphaCodeEmitter {
MachineCodeEmitter &MCE;
public:
@ -60,7 +60,7 @@ namespace {
public:
static char ID;
explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
: MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
: MachineFunctionPass(&ID), AlphaCodeEmitter(mce),
II(0), TM(tm), MCE(mce) {}
Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii)
: MachineFunctionPass(&ID), AlphaCodeEmitter(mce),

128
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -48,9 +48,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
//I am having problems with shr n i8 1
setShiftAmountType(MVT::i64);
setBooleanContents(ZeroOrOneBooleanContent);
setUsesGlobalOffsetTable(true);
addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
@ -60,10 +60,10 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
@ -73,13 +73,13 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
// setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
@ -93,7 +93,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BSWAP , MVT::i64, Expand);
setOperationAction(ISD::ROTL , MVT::i64, Expand);
setOperationAction(ISD::ROTR , MVT::i64, Expand);
setOperationAction(ISD::SREM , MVT::i64, Custom);
setOperationAction(ISD::UREM , MVT::i64, Custom);
setOperationAction(ISD::SDIV , MVT::i64, Custom);
@ -134,7 +134,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
@ -202,7 +202,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
@ -403,7 +403,7 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
unsigned args_float[] = {
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
SDValue argt;
EVT ObjectVT = Ins[ArgNo].VT;
@ -414,17 +414,17 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
default:
assert(false && "Invalid value type!");
case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F8RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
case MVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
&Alpha::F4RCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
break;
case MVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
&Alpha::GPRCRegClass);
ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
break;
@ -495,7 +495,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
assert(ArgVT.isFloatingPoint());
ArgReg = Alpha::F0;
}
Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
Outs[0].Val, Copy.getValue(1));
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
@ -512,22 +512,22 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
ArgReg1 = Alpha::F0;
ArgReg2 = Alpha::F1;
}
Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
Outs[0].Val, Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
Outs[1].Val, Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
break;
}
}
return DAG.getNode(AlphaISD::RET_FLAG, dl,
return DAG.getNode(AlphaISD::RET_FLAG, dl,
MVT::Other, Copy, Copy.getValue(1));
}
@ -573,7 +573,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (IntNo) {
default: break; // Don't custom lower most intrinsics.
case Intrinsic::alpha_umulh:
return DAG.getNode(ISD::MULHU, dl, MVT::i64,
return DAG.getNode(ISD::MULHU, dl, MVT::i64,
Op.getOperand(1), Op.getOperand(2));
}
}
@ -582,14 +582,14 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
DAG.getConstant(64, MVT::i64), ShAmt);
SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
DAG.getConstant(64, MVT::i64), ShAmt);
SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
DAG.getConstant(0, MVT::i64), ISD::SETLE);
// if 64 - shAmt <= 0
SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
DAG.getConstant(0, MVT::i64), bm);
DAG.getConstant(0, MVT::i64), bm);
SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
// else
SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
@ -601,7 +601,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
SDValue Ops[2] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);
}
}
// case ISD::SRA_PARTS:
// case ISD::SHL_PARTS:
@ -623,7 +623,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
if (!isDouble) //Promote
src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src);
@ -633,7 +633,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
Constant *C = CP->getConstVal();
SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
// FIXME there isn't really any debug info here
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
@ -654,11 +654,11 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
}
case ISD::ExternalSymbol: {
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
->getSymbol(), MVT::i64),
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
@ -681,7 +681,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::UDIV:
if (Op.getValueType().isInteger()) {
if (Op.getOperand(1).getOpcode() == ISD::Constant)
return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
: BuildUDIV(Op.getNode(), DAG, NULL);
const char* opstr = 0;
switch (Op.getOpcode()) {
@ -715,12 +715,12 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue SrcP = Op.getOperand(2);
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
NP, NULL,0, MVT::i32);
SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
@ -730,7 +730,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0);
SDValue VAListP = Op.getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
@ -739,13 +739,13 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:
case ISD::RETURNADDR:
return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(),
MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
}
return SDValue();
}
@ -769,7 +769,7 @@ void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
AlphaTargetLowering::ConstraintType
AlphaTargetLowering::ConstraintType
AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
@ -788,33 +788,33 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break; // Unknown constriant letter
case 'f':
case 'f':
return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
Alpha::F3 , Alpha::F4 , Alpha::F5 ,
Alpha::F6 , Alpha::F7 , Alpha::F8 ,
Alpha::F9 , Alpha::F10, Alpha::F11,
Alpha::F12, Alpha::F13, Alpha::F14,
Alpha::F15, Alpha::F16, Alpha::F17,
Alpha::F18, Alpha::F19, Alpha::F20,
Alpha::F21, Alpha::F22, Alpha::F23,
Alpha::F24, Alpha::F25, Alpha::F26,
Alpha::F27, Alpha::F28, Alpha::F29,
Alpha::F6 , Alpha::F7 , Alpha::F8 ,
Alpha::F9 , Alpha::F10, Alpha::F11,
Alpha::F12, Alpha::F13, Alpha::F14,
Alpha::F15, Alpha::F16, Alpha::F17,
Alpha::F18, Alpha::F19, Alpha::F20,
Alpha::F21, Alpha::F22, Alpha::F23,
Alpha::F24, Alpha::F25, Alpha::F26,
Alpha::F27, Alpha::F28, Alpha::F29,
Alpha::F30, Alpha::F31, 0);
case 'r':
return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
Alpha::R3 , Alpha::R4 , Alpha::R5 ,
Alpha::R6 , Alpha::R7 , Alpha::R8 ,
Alpha::R9 , Alpha::R10, Alpha::R11,
Alpha::R12, Alpha::R13, Alpha::R14,
Alpha::R15, Alpha::R16, Alpha::R17,
Alpha::R18, Alpha::R19, Alpha::R20,
Alpha::R21, Alpha::R22, Alpha::R23,
Alpha::R24, Alpha::R25, Alpha::R26,
Alpha::R27, Alpha::R28, Alpha::R29,
case 'r':
return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
Alpha::R3 , Alpha::R4 , Alpha::R5 ,
Alpha::R6 , Alpha::R7 , Alpha::R8 ,
Alpha::R9 , Alpha::R10, Alpha::R11,
Alpha::R12, Alpha::R13, Alpha::R14,
Alpha::R15, Alpha::R16, Alpha::R17,
Alpha::R18, Alpha::R19, Alpha::R20,
Alpha::R21, Alpha::R22, Alpha::R23,
Alpha::R24, Alpha::R25, Alpha::R26,
Alpha::R27, Alpha::R28, Alpha::R29,
Alpha::R30, Alpha::R31, 0);
}
}
return std::vector<unsigned>();
}
//===----------------------------------------------------------------------===//
@ -834,10 +834,10 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MI->getOpcode() == Alpha::SWAP64) &&
"Unexpected instr type to insert");
bool is32 = MI->getOpcode() == Alpha::CAS32 ||
bool is32 = MI->getOpcode() == Alpha::CAS32 ||
MI->getOpcode() == Alpha::LAS32 ||
MI->getOpcode() == Alpha::SWAP32;
//Load locked store conditional for atomic ops take on the same form
//start:
//ll
@ -849,14 +849,14 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
DebugLoc dl = MI->getDebugLoc();
MachineFunction::iterator It = BB;
++It;
MachineBasicBlock *thisMBB = BB;
MachineFunction *F = BB->getParent();
MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
// Inform sdisel of the edge changes.
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
E = BB->succ_end(); I != E; ++I)
EM->insert(std::make_pair(*I, sinkMBB));
@ -866,18 +866,18 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
F->insert(It, sinkMBB);
BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
unsigned reg_res = MI->getOperand(0).getReg(),
reg_ptr = MI->getOperand(1).getReg(),
reg_v2 = MI->getOperand(2).getReg(),
reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
reg_res).addImm(0).addReg(reg_ptr);
switch (MI->getOpcode()) {
case Alpha::CAS32:
case Alpha::CAS64: {
unsigned reg_cmp
unsigned reg_cmp
= F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
.addReg(reg_v2).addReg(reg_res);

4
lib/Target/Blackfin/BlackfinISelLowering.cpp
View File

@ -173,7 +173,7 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
ArgLocs, *DAG.getContext());
CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
@ -286,7 +286,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
*DAG.getContext());
CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
// Get the size of the outgoing arguments stack space requirement.

12
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -90,7 +90,7 @@ namespace {
template <class CodeEmitter>
char Emitter<CodeEmitter>::ID = 0;
}
/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
/// to the specified MCE object.
@ -129,7 +129,7 @@ bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
template <class CodeEmitter>
void Emitter<CodeEmitter>::emitBasicBlock(MachineBasicBlock &MBB) {
MCE.StartMachineBasicBlock(&MBB);
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
const MachineInstr &MI = *I;
MCE.processDebugLoc(MI.getDebugLoc());
@ -202,7 +202,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
case PPC::LWZ8:
case PPC::LFS:
case PPC::LFD:
// Stores.
case PPC::STB:
case PPC::STB8:
@ -223,7 +223,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
break;
}
}
MachineRelocation R;
if (MO.isGlobal()) {
R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
@ -240,7 +240,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, MO.getIndex(), 0);
}
// If in PIC mode, we need to encode the negated address of the
// 'movepctolr' into the unrelocated field. After relocation, we'll have
// &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
@ -251,7 +251,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
R.setConstantVal(-(intptr_t)MovePCtoLROffset - 4);
}
MCE.addRelocation(R);
} else if (MO.isMBB()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();

20
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7668,7 +7668,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
// all of this code can be replaced with that in the .td file.
MachineBasicBlock *
X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
unsigned numArgs, bool memArg) const {
unsigned numArgs, bool memArg) const {
MachineFunction *F = BB->getParent();
DebugLoc dl = MI->getDebugLoc();
@ -7771,7 +7771,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
// To "insert" a SELECT_CC instruction, we actually have to insert the
// diamond control-flow pattern. The incoming instruction knows the
// destination vreg to set, the condition code register to branch on, the
@ -7779,7 +7779,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineFunction::iterator It = BB;
++It;
// thisMBB:
// ...
// TrueVal = ...
@ -7798,7 +7798,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
// Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
// Also inform sdisel of the edge changes.
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
E = BB->succ_end(); I != E; ++I) {
EM->insert(std::make_pair(*I, sinkMBB));
sinkMBB->addSuccessor(*I);
@ -7810,15 +7810,15 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
// Add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
BB = copy0MBB;
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
@ -9374,12 +9374,12 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
(Constraint[4] >= '0' && Constraint[4] <= '7') &&
Constraint[5] == ')' &&
Constraint[6] == '}') {
Res.first = X86::ST0+Constraint[4]-'0';
Res.second = X86::RFP80RegisterClass;
return Res;
}
// GCC allows "st(0)" to be called just plain "st".
if (StringsEqualNoCase("{st}", Constraint)) {
Res.first = X86::ST0;
@ -9393,7 +9393,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Res.second = X86::CCRRegisterClass;
return Res;
}
// 'A' means EAX + EDX.
if (Constraint == "A") {
Res.first = X86::EAX;

10
lib/Transforms/IPO/MergeFunctions.cpp
View File

@ -582,19 +582,19 @@ static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) {
llvm_unreachable(0);
// fall-through
case ExternalWeak:
if (F->hasAddressTaken())
if (F->hasAddressTaken())
ThunkGToF(F, G);
else
AliasGToF(F, G);
break;
break;
case Internal: {
bool addrTakenF = F->hasAddressTaken();
bool addrTakenG = G->hasAddressTaken();
if (!addrTakenF && addrTakenG) {
std::swap(FnVec[i], FnVec[j]);
std::swap(F, G);
std::swap(addrTakenF, addrTakenG);
}
std::swap(addrTakenF, addrTakenG);
}
if (addrTakenF && addrTakenG) {
ThunkGToF(F, G);
@ -602,7 +602,7 @@ static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) {
assert(!addrTakenG);
AliasGToF(F, G);
}
} break;
} break;
}
break;
}

422
lib/Transforms/Scalar/GVN.cpp
View File

File diff suppressed because it is too large Load Diff

238
lib/VMCore/AsmWriter.cpp
View File

@ -50,15 +50,15 @@ AssemblyAnnotationWriter::~AssemblyAnnotationWriter() {}
static const Module *getModuleFromVal(const Value *V) {
if (const Argument *MA = dyn_cast<Argument>(V))
return MA->getParent() ? MA->getParent()->getParent() : 0;
if (const BasicBlock *BB = dyn_cast<BasicBlock>(V))
return BB->getParent() ? BB->getParent()->getParent() : 0;
if (const Instruction *I = dyn_cast<Instruction>(V)) {
const Function *M = I->getParent() ? I->getParent()->getParent() : 0;
return M ? M->getParent() : 0;
}
if (const GlobalValue *GV = dyn_cast<GlobalValue>(V))
return GV->getParent();
return 0;
@ -97,7 +97,7 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
case LabelPrefix: break;
case LocalPrefix: OS << '%'; break;
}
// Scan the name to see if it needs quotes first.
bool NeedsQuotes = isdigit(Name[0]);
if (!NeedsQuotes) {
@ -109,13 +109,13 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
}
}
}
// If we didn't need any quotes, just write out the name in one blast.
if (!NeedsQuotes) {
OS << Name;
return;
}
// Okay, we need quotes. Output the quotes and escape any scary characters as
// needed.
OS << '"';
@ -127,7 +127,7 @@ static void PrintLLVMName(raw_ostream &OS, const StringRef &Name,
/// prefixed with % (if the string only contains simple characters) or is
/// surrounded with ""'s (if it has special chars in it). Print it out.
static void PrintLLVMName(raw_ostream &OS, const Value *V) {
PrintLLVMName(OS, V->getName(),
PrintLLVMName(OS, V->getName(),
isa<GlobalValue>(V) ? GlobalPrefix : LocalPrefix);
}
@ -174,11 +174,11 @@ void TypePrinting::CalcTypeName(const Type *Ty,
return;
}
}
// Check to see if the Type is already on the stack...
unsigned Slot = 0, CurSize = TypeStack.size();
while (Slot < CurSize && TypeStack[Slot] != Ty) ++Slot; // Scan for type
// This is another base case for the recursion. In this case, we know
// that we have looped back to a type that we have previously visited.
// Generate the appropriate upreference to handle this.
@ -186,9 +186,9 @@ void TypePrinting::CalcTypeName(const Type *Ty,
OS << '\\' << unsigned(CurSize-Slot); // Here's the upreference
return;
}
TypeStack.push_back(Ty); // Recursive case: Add us to the stack..
switch (Ty->getTypeID()) {
case Type::VoidTyID: OS << "void"; break;
case Type::FloatTyID: OS << "float"; break;
@ -201,7 +201,7 @@ void TypePrinting::CalcTypeName(const Type *Ty,
case Type::IntegerTyID:
OS << 'i' << cast<IntegerType>(Ty)->getBitWidth();
break;
case Type::FunctionTyID: {
const FunctionType *FTy = cast<FunctionType>(Ty);
CalcTypeName(FTy->getReturnType(), TypeStack, OS);
@ -265,7 +265,7 @@ void TypePrinting::CalcTypeName(const Type *Ty,
OS << "<unrecognized-type>";
break;
}
TypeStack.pop_back(); // Remove self from stack.
}
@ -283,13 +283,13 @@ void TypePrinting::print(const Type *Ty, raw_ostream &OS,
return;
}
}
// Otherwise we have a type that has not been named but is a derived type.
// Carefully recurse the type hierarchy to print out any contained symbolic
// names.
SmallVector<const Type *, 16> TypeStack;
std::string TypeName;
raw_string_ostream TypeOS(TypeName);
CalcTypeName(Ty, TypeStack, TypeOS, IgnoreTopLevelName);
OS << TypeOS.str();
@ -305,13 +305,13 @@ namespace {
// objects, we keep several helper maps.
DenseSet<const Value*> VisitedConstants;
DenseSet<const Type*> VisitedTypes;
TypePrinting &TP;
std::vector<const Type*> &NumberedTypes;
public:
TypeFinder(TypePrinting &tp, std::vector<const Type*> &numberedTypes)
: TP(tp), NumberedTypes(numberedTypes) {}
void Run(const Module &M) {
// Get types from the type symbol table. This gets opaque types referened
// only through derived named types.
@ -319,7 +319,7 @@ namespace {
for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end();
TI != E; ++TI)
IncorporateType(TI->second);
// Get types from global variables.
for (Module::const_global_iterator I = M.global_begin(),
E = M.global_end(); I != E; ++I) {
@ -327,18 +327,18 @@ namespace {
if (I->hasInitializer())
IncorporateValue(I->getInitializer());
}
// Get types from aliases.
for (Module::const_alias_iterator I = M.alias_begin(),
E = M.alias_end(); I != E; ++I) {
IncorporateType(I->getType());
IncorporateValue(I->getAliasee());
}
// Get types from functions.
for (Module::const_iterator FI = M.begin(), E = M.end(); FI != E; ++FI) {
IncorporateType(FI->getType());
for (Function::const_iterator BB = FI->begin(), E = FI->end();
BB != E;++BB)
for (BasicBlock::const_iterator II = BB->begin(),
@ -352,40 +352,40 @@ namespace {
}
}
}
private:
void IncorporateType(const Type *Ty) {
// Check to see if we're already visited this type.
if (!VisitedTypes.insert(Ty).second)
return;
// If this is a structure or opaque type, add a name for the type.
if (((isa<StructType>(Ty) && cast<StructType>(Ty)->getNumElements())
|| isa<OpaqueType>(Ty)) && !TP.hasTypeName(Ty)) {
TP.addTypeName(Ty, "%"+utostr(unsigned(NumberedTypes.size())));
NumberedTypes.push_back(Ty);
}
// Recursively walk all contained types.
for (Type::subtype_iterator I = Ty->subtype_begin(),
E = Ty->subtype_end(); I != E; ++I)
IncorporateType(*I);
IncorporateType(*I);
}
/// IncorporateValue - This method is used to walk operand lists finding
/// types hiding in constant expressions and other operands that won't be
/// walked in other ways. GlobalValues, basic blocks, instructions, and
/// inst operands are all explicitly enumerated.
void IncorporateValue(const Value *V) {
if (V == 0 || !isa<Constant>(V) || isa<GlobalValue>(V)) return;
// Already visited?
if (!VisitedConstants.insert(V).second)
return;
// Check this type.
IncorporateType(V->getType());
// Look in operands for types.
const Constant *C = cast<Constant>(V);
for (Constant::const_op_iterator I = C->op_begin(),
@ -399,18 +399,18 @@ namespace {
/// AddModuleTypesToPrinter - Add all of the symbolic type names for types in
/// the specified module to the TypePrinter and all numbered types to it and the
/// NumberedTypes table.
static void AddModuleTypesToPrinter(TypePrinting &TP,
static void AddModuleTypesToPrinter(TypePrinting &TP,
std::vector<const Type*> &NumberedTypes,
const Module *M) {
if (M == 0) return;
// If the module has a symbol table, take all global types and stuff their
// names into the TypeNames map.
const TypeSymbolTable &ST = M->getTypeSymbolTable();
for (TypeSymbolTable::const_iterator TI = ST.begin(), E = ST.end();
TI != E; ++TI) {
const Type *Ty = cast<Type>(TI->second);
// As a heuristic, don't insert pointer to primitive types, because
// they are used too often to have a single useful name.
if (const PointerType *PTy = dyn_cast<PointerType>(Ty)) {
@ -419,11 +419,11 @@ static void AddModuleTypesToPrinter(TypePrinting &TP,
!isa<OpaqueType>(PETy))
continue;
}
// Likewise don't insert primitives either.
if (Ty->isInteger() || Ty->isPrimitiveType())
continue;
// Get the name as a string and insert it into TypeNames.
std::string NameStr;
raw_string_ostream NameROS(NameStr);
@ -432,7 +432,7 @@ static void AddModuleTypesToPrinter(TypePrinting &TP,
NameOS.flush();
TP.addTypeName(Ty, NameStr);
}
// Walk the entire module to find references to unnamed structure and opaque
// types. This is required for correctness by opaque types (because multiple
// uses of an unnamed opaque type needs to be referred to by the same ID) and
@ -464,15 +464,15 @@ class SlotTracker {
public:
/// ValueMap - A mapping of Values to slot numbers.
typedef DenseMap<const Value*, unsigned> ValueMap;
private:
private:
/// TheModule - The module for which we are holding slot numbers.
const Module* TheModule;
/// TheFunction - The function for which we are holding slot numbers.
const Function* TheFunction;
bool FunctionProcessed;
/// TheMDNode - The MDNode for which we are holding slot numbers.
const MDNode *TheMDNode;
@ -482,11 +482,11 @@ private:
/// mMap - The TypePlanes map for the module level data.
ValueMap mMap;
unsigned mNext;
/// fMap - The TypePlanes map for the function level data.
ValueMap fMap;
unsigned fNext;
/// mdnMap - Map for MDNodes.
ValueMap mdnMap;
unsigned mdnNext;
@ -561,22 +561,22 @@ private:
static SlotTracker *createSlotTracker(const Value *V) {
if (const Argument *FA = dyn_cast<Argument>(V))
return new SlotTracker(FA->getParent());
if (const Instruction *I = dyn_cast<Instruction>(V))
return new SlotTracker(I->getParent()->getParent());
if (const BasicBlock *BB = dyn_cast<BasicBlock>(V))
return new SlotTracker(BB->getParent());
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(V))
return new SlotTracker(GV->getParent());
if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(V))
return new SlotTracker(GA->getParent());
return new SlotTracker(GA->getParent());
if (const Function *Func = dyn_cast<Function>(V))
return new SlotTracker(Func);
return 0;
}
@ -617,7 +617,7 @@ inline void SlotTracker::initialize() {
processModule();
TheModule = 0; ///< Prevent re-processing next time we're called.
}
if (TheFunction && !FunctionProcessed)
processFunction();
@ -632,20 +632,20 @@ inline void SlotTracker::initialize() {
// variable initializers and create slots for them.
void SlotTracker::processModule() {
ST_DEBUG("begin processModule!\n");
// Add all of the unnamed global variables to the value table.
for (Module::const_global_iterator I = TheModule->global_begin(),
E = TheModule->global_end(); I != E; ++I) {
if (!I->hasName())
if (!I->hasName())
CreateModuleSlot(I);
if (I->hasInitializer()) {
if (MDNode *N = dyn_cast<MDNode>(I->getInitializer()))
if (MDNode *N = dyn_cast<MDNode>(I->getInitializer()))
CreateMetadataSlot(N);
}
}
// Add metadata used by named metadata.
for (Module::const_named_metadata_iterator
for (Module::const_named_metadata_iterator
I = TheModule->named_metadata_begin(),
E = TheModule->named_metadata_end(); I != E; ++I) {
const NamedMDNode *NMD = I;
@ -661,7 +661,7 @@ void SlotTracker::processModule() {
I != E; ++I)
if (!I->hasName())
CreateModuleSlot(I);
ST_DEBUG("end processModule!\n");
}
@ -669,15 +669,15 @@ void SlotTracker::processModule() {
void SlotTracker::processFunction() {
ST_DEBUG("begin processFunction!\n");
fNext = 0;
// Add all the function arguments with no names.
for(Function::const_arg_iterator AI = TheFunction->arg_begin(),
AE = TheFunction->arg_end(); AI != AE; ++AI)
if (!AI->hasName())
CreateFunctionSlot(AI);
ST_DEBUG("Inserting Instructions:\n");
Metadata &TheMetadata = TheFunction->getContext().getMetadata();
// Add all of the basic blocks and instructions with no names.
@ -685,27 +685,27 @@ void SlotTracker::processFunction() {
E = TheFunction->end(); BB != E; ++BB) {
if (!BB->hasName())
CreateFunctionSlot(BB);
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E;
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E;
++I) {
if (I->getType() != Type::getVoidTy(TheFunction->getContext()) &&
!I->hasName())
CreateFunctionSlot(I);
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (MDNode *N = dyn_cast_or_null<MDNode>(I->getOperand(i)))
CreateMetadataSlot(N);
// Process metadata attached with this instruction.
const Metadata::MDMapTy *MDs = TheMetadata.getMDs(I);
if (MDs)
for (Metadata::MDMapTy::const_iterator MI = MDs->begin(),
ME = MDs->end(); MI != ME; ++MI)
if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
CreateMetadataSlot(MDN);
for (Metadata::MDMapTy::const_iterator MI = MDs->begin(),
ME = MDs->end(); MI != ME; ++MI)
if (MDNode *MDN = dyn_cast_or_null<MDNode>(MI->second))
CreateMetadataSlot(MDN);
}
}
FunctionProcessed = true;
ST_DEBUG("end processFunction!\n");
}
@ -746,7 +746,7 @@ void SlotTracker::purgeFunction() {
int SlotTracker::getGlobalSlot(const GlobalValue *V) {
// Check for uninitialized state and do lazy initialization.
initialize();
// Find the type plane in the module map
ValueMap::iterator MI = mMap.find(V);
return MI == mMap.end() ? -1 : (int)MI->second;
@ -756,7 +756,7 @@ int SlotTracker::getGlobalSlot(const GlobalValue *V) {
int SlotTracker::getMetadataSlot(const MDNode *N) {
// Check for uninitialized state and do lazy initialization.
initialize();
// Find the type plane in the module map
ValueMap::iterator MI = mdnMap.find(N);
return MI == mdnMap.end() ? -1 : (int)MI->second;
@ -766,10 +766,10 @@ int SlotTracker::getMetadataSlot(const MDNode *N) {
/// getLocalSlot - Get the slot number for a value that is local to a function.
int SlotTracker::getLocalSlot(const Value *V) {
assert(!isa<Constant>(V) && "Can't get a constant or global slot with this!");
// Check for uninitialized state and do lazy initialization.
initialize();
ValueMap::iterator FI = fMap.find(V);
return FI == fMap.end() ? -1 : (int)FI->second;
}
@ -778,13 +778,13 @@ int SlotTracker::getLocalSlot(const Value *V) {
/// CreateModuleSlot - Insert the specified GlobalValue* into the slot table.
void SlotTracker::CreateModuleSlot(const GlobalValue *V) {
assert(V && "Can't insert a null Value into SlotTracker!");
assert(V->getType() != Type::getVoidTy(V->getContext()) &&
assert(V->getType() != Type::getVoidTy(V->getContext()) &&
"Doesn't need a slot!");
assert(!V->hasName() && "Doesn't need a slot!");
unsigned DestSlot = mNext++;
mMap[V] = DestSlot;
ST_DEBUG(" Inserting value [" << V->getType() << "] = " << V << " slot=" <<
DestSlot << " [");
// G = Global, F = Function, A = Alias, o = other
@ -795,21 +795,21 @@ void SlotTracker::CreateModuleSlot(const GlobalValue *V) {
/// CreateSlot - Create a new slot for the specified value if it has no name.
void SlotTracker::CreateFunctionSlot(const Value *V) {
assert(V->getType() != Type::getVoidTy(TheFunction->getContext()) &&
assert(V->getType() != Type::getVoidTy(TheFunction->getContext()) &&
!V->hasName() && "Doesn't need a slot!");
unsigned DestSlot = fNext++;
fMap[V] = DestSlot;
// G = Global, F = Function, o = other
ST_DEBUG(" Inserting value [" << V->getType() << "] = " << V << " slot=" <<
DestSlot << " [o]\n");
}
}
/// CreateModuleSlot - Insert the specified MDNode* into the slot table.
void SlotTracker::CreateMetadataSlot(const MDNode *N) {
assert(N && "Can't insert a null Value into SlotTracker!");
ValueMap::iterator I = mdnMap.find(N);
if (I != mdnMap.end())
return;
@ -817,11 +817,11 @@ void SlotTracker::CreateMetadataSlot(const MDNode *N) {
unsigned DestSlot = mdnNext++;
mdnMap[N] = DestSlot;
for (MDNode::const_elem_iterator MDI = N->elem_begin(),
for (MDNode::const_elem_iterator MDI = N->elem_begin(),
MDE = N->elem_end(); MDI != MDE; ++MDI) {
const Value *TV = *MDI;
if (TV)
if (const MDNode *N2 = dyn_cast<MDNode>(TV))
if (const MDNode *N2 = dyn_cast<MDNode>(TV))
CreateMetadataSlot(N2);
}
}
@ -873,15 +873,15 @@ static void WriteMDNodes(formatted_raw_ostream &Out, TypePrinting &TypePrinter,
SlotTracker &Machine) {
SmallVector<const MDNode *, 16> Nodes;
Nodes.resize(Machine.mdnSize());
for (SlotTracker::ValueMap::iterator I =
Machine.mdnBegin(), E = Machine.mdnEnd(); I != E; ++I)
for (SlotTracker::ValueMap::iterator I =
Machine.mdnBegin(), E = Machine.mdnEnd(); I != E; ++I)
Nodes[I->second] = cast<MDNode>(I->first);
for (unsigned i = 0, e = Nodes.size(); i != e; ++i) {
Out << '!' << i << " = metadata ";
const MDNode *Node = Nodes[i];
Out << "!{";
for (MDNode::const_elem_iterator NI = Node->elem_begin(),
for (MDNode::const_elem_iterator NI = Node->elem_begin(),
NE = Node->elem_end(); NI != NE;) {
const Value *V = *NI;
if (!V)
@ -928,7 +928,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << CI->getValue();
return;
}
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
if (&CFP->getValueAPF().getSemantics() == &APFloat::IEEEdouble ||
&CFP->getValueAPF().getSemantics() == &APFloat::IEEEsingle) {
@ -966,14 +966,14 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
APFloat apf = CFP->getValueAPF();
// Floats are represented in ASCII IR as double, convert.
if (!isDouble)
apf.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
apf.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
&ignored);
Out << "0x" <<
utohex_buffer(uint64_t(apf.bitcastToAPInt().getZExtValue()),
Out << "0x" <<
utohex_buffer(uint64_t(apf.bitcastToAPInt().getZExtValue()),
Buffer+40);
return;
}
// Some form of long double. These appear as a magic letter identifying
// the type, then a fixed number of hex digits.
Out << "0x";
@ -1026,12 +1026,12 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
return;
}
if (isa<ConstantAggregateZero>(CV)) {
Out << "zeroinitializer";
return;
}
if (const ConstantArray *CA = dyn_cast<ConstantArray>(CV)) {
// As a special case, print the array as a string if it is an array of
// i8 with ConstantInt values.
@ -1059,7 +1059,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
return;
}
if (const ConstantStruct *CS = dyn_cast<ConstantStruct>(CV)) {
if (CS->getType()->isPacked())
Out << '<';
@ -1081,13 +1081,13 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
}
Out << ' ';
}
Out << '}';
if (CS->getType()->isPacked())
Out << '>';
return;
}
if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) {
const Type *ETy = CP->getType()->getElementType();
assert(CP->getNumOperands() > 0 &&
@ -1105,17 +1105,17 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << '>';
return;
}
if (isa<ConstantPointerNull>(CV)) {
Out << "null";
return;
}
if (isa<UndefValue>(CV)) {
Out << "undef";
return;
}
if (const MDNode *Node = dyn_cast<MDNode>(CV)) {
Out << "!" << Machine->getMetadataSlot(Node);
return;
@ -1150,7 +1150,7 @@ static void WriteConstantInt(raw_ostream &Out, const Constant *CV,
Out << ')';
return;
}
Out << "<placeholder or erroneous Constant>";
}
@ -1166,14 +1166,14 @@ static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
PrintLLVMName(Out, V);
return;
}
const Constant *CV = dyn_cast<Constant>(V);
if (CV && !isa<GlobalValue>(CV)) {
assert(TypePrinter && "Constants require TypePrinting!");
WriteConstantInt(Out, CV, *TypePrinter, Machine);
return;
}
if (const InlineAsm *IA = dyn_cast<InlineAsm>(V)) {
Out << "asm ";
if (IA->hasSideEffects())
@ -1221,7 +1221,7 @@ static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
Slot = -1;
}
}
if (Slot != -1)
Out << Prefix << Slot;
else
@ -1275,7 +1275,7 @@ public:
}
void write(const Module *M) { printModule(M); }
void write(const GlobalValue *G) {
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(G))
printGlobal(GV);
@ -1286,7 +1286,7 @@ public:
else
llvm_unreachable("Unknown global");
}
void write(const BasicBlock *BB) { printBasicBlock(BB); }
void write(const Instruction *I) { printInstruction(*I); }
@ -1322,7 +1322,7 @@ void AssemblyWriter::writeOperand(const Value *Operand, bool PrintType) {
}
}
void AssemblyWriter::writeParamOperand(const Value *Operand,
void AssemblyWriter::writeParamOperand(const Value *Operand,
Attributes Attrs) {
if (Operand == 0) {
Out << "<null operand!>";
@ -1370,7 +1370,7 @@ void AssemblyWriter::printModule(const Module *M) {
PrintEscapedString(std::string(Asm.begin()+CurPos, Asm.end()), Out);
Out << "\"\n";
}
// Loop over the dependent libraries and emit them.
Module::lib_iterator LI = M->lib_begin();
Module::lib_iterator LE = M->lib_end();
@ -1395,7 +1395,7 @@ void AssemblyWriter::printModule(const Module *M) {
for (Module::const_global_iterator I = M->global_begin(), E = M->global_end();
I != E; ++I)
printGlobal(I);
// Output all aliases.
if (!M->alias_empty()) Out << "\n";
for (Module::const_alias_iterator I = M->alias_begin(), E = M->alias_end();
@ -1466,7 +1466,7 @@ void AssemblyWriter::printGlobal(const GlobalVariable *GV) {
if (!GV->hasInitializer() && GV->hasExternalLinkage())
Out << "external ";
PrintLinkage(GV->getLinkage(), Out);
PrintVisibility(GV->getVisibility(), Out);
@ -1480,7 +1480,7 @@ void AssemblyWriter::printGlobal(const GlobalVariable *GV) {
Out << ' ';
writeOperand(GV->getInitializer(), false);
}
if (GV->hasSection())
Out << ", section \"" << GV->getSection() << '"';
if (GV->getAlignment())
@ -1503,9 +1503,9 @@ void AssemblyWriter::printAlias(const GlobalAlias *GA) {
Out << "alias ";
PrintLinkage(GA->getLinkage(), Out);
const Constant *Aliasee = GA->getAliasee();
if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(Aliasee)) {
TypePrinter.print(GV->getType(), Out);
Out << ' ';
@ -1527,7 +1527,7 @@ void AssemblyWriter::printAlias(const GlobalAlias *GA) {
"Unsupported aliasee");
writeOperand(CE, false);
}
printInfoComment(*GA);
Out << '\n';
}
@ -1536,13 +1536,13 @@ void AssemblyWriter::printTypeSymbolTable(const TypeSymbolTable &ST) {
// Emit all numbered types.
for (unsigned i = 0, e = NumberedTypes.size(); i != e; ++i) {
Out << '%' << i << " = type ";
// Make sure we print out at least one level of the type structure, so
// that we do not get %2 = type %2
TypePrinter.printAtLeastOneLevel(NumberedTypes[i], Out);
Out << '\n';
}
// Print the named types.
for (TypeSymbolTable::const_iterator TI = ST.begin(), TE = ST.end();
TI != TE; ++TI) {
@ -1568,7 +1568,7 @@ void AssemblyWriter::printFunction(const Function *F) {
Out << "declare ";
else
Out << "define ";
PrintLinkage(F->getLinkage(), Out);
PrintVisibility(F->getVisibility(), Out);
@ -1613,10 +1613,10 @@ void AssemblyWriter::printFunction(const Function *F) {
for (unsigned i = 0, e = FT->getNumParams(); i != e; ++i) {
// Insert commas as we go... the first arg doesn't get a comma
if (i) Out << ", ";
// Output type...
TypePrinter.print(FT->getParamType(i), Out);
Attributes ArgAttrs = Attrs.getParamAttributes(i+1);
if (ArgAttrs != Attribute::None)
Out << ' ' << Attribute::getAsString(ArgAttrs);
@ -1656,7 +1656,7 @@ void AssemblyWriter::printFunction(const Function *F) {
/// printArgument - This member is called for every argument that is passed into
/// the function. Simply print it out
///
void AssemblyWriter::printArgument(const Argument *Arg,
void AssemblyWriter::printArgument(const Argument *Arg,
Attributes Attrs) {
// Output type...
TypePrinter.print(Arg->getType(), Out);
@ -1696,7 +1696,7 @@ void AssemblyWriter::printBasicBlock(const BasicBlock *BB) {
Out.PadToColumn(50);
Out << ";";
pred_const_iterator PI = pred_begin(BB), PE = pred_end(BB);
if (PI == PE) {
Out << " No predecessors!";
} else {
@ -1982,7 +1982,7 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
writeOperand(I.getOperand(i), PrintAllTypes);
}
}
// Print post operand alignment for load/store
if (isa<LoadInst>(I) && cast<LoadInst>(I).getAlignment()) {
Out << ", align " << cast<LoadInst>(I).getAlignment();
@ -2060,7 +2060,7 @@ void Value::print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW) const {
MDNode *MD = dyn_cast_or_null<MDNode>(N->getElement(i));
if (MD)
OS << '!' << SlotTable.getMetadataSlot(MD);
else
else
OS << "null";
}
OS << "}\n";

8
lib/VMCore/Instruction.cpp
View File

@ -292,11 +292,11 @@ bool Instruction::isUsedOutsideOfBlock(const BasicBlock *BB) const {
return true;
continue;
}
if (PN->getIncomingBlock(UI) != BB)
return true;
}
return false;
return false;
}
/// mayReadFromMemory - Return true if this instruction may read memory.
@ -380,8 +380,8 @@ bool Instruction::isCommutative(unsigned op) {
static bool isMalloc(const Value* I) {
const CallInst *CI = dyn_cast<CallInst>(I);
if (!CI) {
const BitCastInst *BCI = dyn_cast<BitCastInst>(I);
if (!BCI) return false;
const BitCastInst *BCI = dyn_cast<BitCastInst>(I);
if (!BCI) return false;
CI = dyn_cast<CallInst>(BCI->getOperand(0));
}