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Revert "[GlobalISel] Combine zext(trunc x) to x"
This reverts commit 4112299ee761a9b6a309c8ff4a7e75f8c8d8851b. Seems to depend on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which is being reverted.
This commit is contained in:
Nico Weber
parent
f0c004a9dc
commit
3784742fd9
@ -316,9 +316,6 @@ public:
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bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
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bool applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
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/// Transform zext(trunc(x)) to x.
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bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg);
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/// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
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bool matchCombineExtOfExt(MachineInstr &MI,
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std::tuple<Register, unsigned> &MatchInfo);
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@ -427,16 +427,6 @@ def anyext_trunc_fold: GICombineRule <
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(apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
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>;
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// Fold (zext (trunc x)) -> x if the source type is same as the destination type
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// and truncated bits are known to be zero.
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def zext_trunc_fold_matchinfo : GIDefMatchData<"Register">;
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def zext_trunc_fold: GICombineRule <
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(defs root:$root, zext_trunc_fold_matchinfo:$matchinfo),
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(match (wip_match_opcode G_ZEXT):$root,
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[{ return Helper.matchCombineZextTrunc(*${root}, ${matchinfo}); }]),
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(apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
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>;
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// Fold ([asz]ext ([asz]ext x)) -> ([asz]ext x).
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def ext_ext_fold_matchinfo : GIDefMatchData<"std::tuple<Register, unsigned>">;
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def ext_ext_fold: GICombineRule <
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@ -593,8 +583,7 @@ def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
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def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p]>;
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def known_bits_simplifications : GICombineGroup<[
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redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask,
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zext_trunc_fold]>;
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redundant_and, redundant_sext_inreg, redundant_or, urem_pow2_to_mask]>;
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def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend]>;
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@ -2295,20 +2295,6 @@ bool CombinerHelper::matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) {
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m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))));
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}
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bool CombinerHelper::matchCombineZextTrunc(MachineInstr &MI, Register &Reg) {
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assert(MI.getOpcode() == TargetOpcode::G_ZEXT && "Expected a G_ZEXT");
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Register DstReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(DstReg);
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if (mi_match(SrcReg, MRI,
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m_GTrunc(m_all_of(m_Reg(Reg), m_SpecificType(DstTy))))) {
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unsigned DstSize = DstTy.getScalarSizeInBits();
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unsigned SrcSize = MRI.getType(SrcReg).getScalarSizeInBits();
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return KB->getKnownBits(Reg).countMinLeadingZeros() >= DstSize - SrcSize;
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}
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return false;
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}
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bool CombinerHelper::matchCombineExtOfExt(
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MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo) {
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assert((MI.getOpcode() == TargetOpcode::G_ANYEXT ||
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@ -1,198 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: zext_trunc_s32_s16_s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_trunc_s32_s16_s32
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; GCN: liveins: $vgpr0
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
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; GCN: %low_bits:_(s32) = G_AND %var, %c3FFF
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; GCN: $vgpr0 = COPY %low_bits(s32)
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%var:_(s32) = COPY $vgpr0
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%c3FFF:_(s32) = G_CONSTANT i32 16383
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%low_bits:_(s32) = G_AND %var, %c3FFF
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%trunc:_(s16) = G_TRUNC %low_bits(s32)
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%zext:_(s32) = G_ZEXT %trunc(s16)
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$vgpr0 = COPY %zext(s32)
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...
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---
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name: zext_trunc_s32_s16_s32_unknown_high_bits
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_trunc_s32_s16_s32_unknown_high_bits
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; GCN: liveins: $vgpr0
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
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; GCN: %low_bits:_(s32) = G_AND %var, %cFFFFF
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; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s32)
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; GCN: %zext:_(s32) = G_ZEXT %trunc(s16)
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; GCN: $vgpr0 = COPY %zext(s32)
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%var:_(s32) = COPY $vgpr0
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%cFFFFF:_(s32) = G_CONSTANT i32 1048575
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%low_bits:_(s32) = G_AND %var, %cFFFFF
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%trunc:_(s16) = G_TRUNC %low_bits(s32)
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%zext:_(s32) = G_ZEXT %trunc(s16)
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$vgpr0 = COPY %zext(s32)
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...
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---
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name: zext_trunc_s64_s16_s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: zext_trunc_s64_s16_s32
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(s64) = COPY $vgpr0_vgpr1
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; GCN: %c3FFF:_(s64) = G_CONSTANT i64 16383
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; GCN: %low_bits:_(s64) = G_AND %var, %c3FFF
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; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s64)
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; GCN: %zext:_(s32) = G_ZEXT %trunc(s16)
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; GCN: $vgpr0 = COPY %zext(s32)
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%var:_(s64) = COPY $vgpr0_vgpr1
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%c3FFF:_(s64) = G_CONSTANT i64 16383
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%low_bits:_(s64) = G_AND %var, %c3FFF
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%trunc:_(s16) = G_TRUNC %low_bits(s64)
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%zext:_(s32) = G_ZEXT %trunc(s16)
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$vgpr0 = COPY %zext(s32)
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...
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---
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name: zext_trunc_s32_s16_s64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_trunc_s32_s16_s64
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; GCN: liveins: $vgpr0
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
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; GCN: %low_bits:_(s32) = G_AND %var, %c3FFF
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; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s32)
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; GCN: %zext:_(s64) = G_ZEXT %trunc(s16)
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; GCN: $vgpr0_vgpr1 = COPY %zext(s64)
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%var:_(s32) = COPY $vgpr0
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%c3FFF:_(s32) = G_CONSTANT i32 16383
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%low_bits:_(s32) = G_AND %var, %c3FFF
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%trunc:_(s16) = G_TRUNC %low_bits(s32)
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%zext:_(s64) = G_ZEXT %trunc(s16)
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$vgpr0_vgpr1 = COPY %zext(s64)
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...
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---
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name: zext_trunc_v2s32_v2s16_v2s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s32
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
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; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
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; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
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; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
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; GCN: $vgpr0_vgpr1 = COPY %low_bits(<2 x s32>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%c3FFF:_(s32) = G_CONSTANT i32 16383
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%c7FFF:_(s32) = G_CONSTANT i32 32767
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%c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
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%low_bits:_(<2 x s32>) = G_AND %var, %c
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%trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
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%zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
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$vgpr0_vgpr1 = COPY %zext(<2 x s32>)
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...
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---
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name: zext_trunc_v2s32_v2s16_v2s32_unknown_high_bits
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s32_unknown_high_bits
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
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; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
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; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %cFFFFF(s32), %c7FFF(s32)
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; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
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; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
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; GCN: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
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; GCN: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%cFFFFF:_(s32) = G_CONSTANT i32 1048575
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%c7FFF:_(s32) = G_CONSTANT i32 32767
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%c:_(<2 x s32>) = G_BUILD_VECTOR %cFFFFF(s32), %c7FFF(s32)
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%low_bits:_(<2 x s32>) = G_AND %var, %c
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%trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
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%zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
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$vgpr0_vgpr1 = COPY %zext(<2 x s32>)
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...
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---
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name: zext_trunc_v2s64_v2s16_v2s32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN-LABEL: name: zext_trunc_v2s64_v2s16_v2s32
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; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN: %c3FFF:_(s64) = G_CONSTANT i64 16383
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; GCN: %c7FFF:_(s64) = G_CONSTANT i64 32767
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; GCN: %c:_(<2 x s64>) = G_BUILD_VECTOR %c3FFF(s64), %c7FFF(s64)
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; GCN: %low_bits:_(<2 x s64>) = G_AND %var, %c
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; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s64>)
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; GCN: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
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; GCN: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
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%var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%c3FFF:_(s64) = G_CONSTANT i64 16383
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%c7FFF:_(s64) = G_CONSTANT i64 32767
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%c:_(<2 x s64>) = G_BUILD_VECTOR %c3FFF(s64), %c7FFF(s64)
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%low_bits:_(<2 x s64>) = G_AND %var, %c
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%trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s64>)
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%zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
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$vgpr0_vgpr1 = COPY %zext(<2 x s32>)
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...
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---
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name: zext_trunc_v2s32_v2s16_v2s64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s64
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
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; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
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; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
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; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
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; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
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; GCN: %zext:_(<2 x s64>) = G_ZEXT %trunc(<2 x s16>)
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; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %zext(<2 x s64>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%c3FFF:_(s32) = G_CONSTANT i32 16383
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%c7FFF:_(s32) = G_CONSTANT i32 32767
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%c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
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%low_bits:_(<2 x s32>) = G_AND %var, %c
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%trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
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%zext:_(<2 x s64>) = G_ZEXT %trunc(<2 x s16>)
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %zext(<2 x s64>)
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...
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@ -404,14 +404,18 @@ define amdgpu_ps i32 @s_shl_i32_zext_i16(i16 inreg %x) {
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX8-NEXT: s_and_b32 s0, s0, 0x3fff
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; GFX8-NEXT: s_lshl_b32 s0, s0, 2
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; GFX8-NEXT: s_bfe_u32 s1, 2, 0x100000
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; GFX8-NEXT: s_lshl_b32 s0, s0, s1
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; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
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; GFX8-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: s_shl_i32_zext_i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX9-NEXT: s_and_b32 s0, s0, 0x3fff
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; GFX9-NEXT: s_lshl_b32 s0, s0, 2
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; GFX9-NEXT: s_bfe_u32 s1, 2, 0x100000
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; GFX9-NEXT: s_lshl_b32 s0, s0, s1
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; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
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; GFX9-NEXT: ; return to shader part epilog
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%and = and i16 %x, 16383
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%ext = zext i16 %and to i32
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@ -460,10 +464,13 @@ define amdgpu_ps <2 x i32> @s_shl_v2i32_zext_v2i16(<2 x i16> inreg %x) {
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; GFX8-LABEL: s_shl_v2i32_zext_v2i16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_movk_i32 s2, 0x3fff
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; GFX8-NEXT: s_mov_b32 s4, 0xffff
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; GFX8-NEXT: s_lshr_b32 s1, s0, 16
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; GFX8-NEXT: s_mov_b32 s3, s2
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; GFX8-NEXT: s_and_b32 s0, s0, 0xffff
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; GFX8-NEXT: s_and_b32 s0, s0, s4
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; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
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; GFX8-NEXT: s_mov_b32 s5, s4
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; GFX8-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5]
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; GFX8-NEXT: s_lshl_b32 s0, s0, 2
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; GFX8-NEXT: s_lshl_b32 s1, s1, 2
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; GFX8-NEXT: ; return to shader part epilog
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