RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

Fix PR8811 by teaching MachineVerifier about optional defs.

Browse Source 
llvm-svn: 122199
This commit is contained in:
Cameron Zwarich 2010-12-19 21:37:23 +00:00
parent 64fbc5e267
commit 37aec9c35d
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/MachineVerifier.cpp
View File

@ -555,6 +555,7 @@ void
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
const MachineInstr *MI = MO->getParent(); const MachineInstr *MI = MO->getParent();
const TargetInstrDesc &TI = MI->getDesc(); const TargetInstrDesc &TI = MI->getDesc();
const TargetOperandInfo &TOI = TI.OpInfo[MONum];
// The first TI.NumDefs operands must be explicit register defines // The first TI.NumDefs operands must be explicit register defines
if (MONum < TI.getNumDefs()) { if (MONum < TI.getNumDefs()) {
@ -568,8 +569,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Don't check if it's the last operand in a variadic instruction. See, // Don't check if it's the last operand in a variadic instruction. See,
// e.g., LDM_RET in the arm back end. // e.g., LDM_RET in the arm back end.
if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) { if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) {
if (MO->isDef()) if (MO->isDef() && !TOI.isOptionalDef())
report("Explicit operand marked as def", MO, MONum); report("Explicit operand marked as def", MO, MONum);
if (MO->isImplicit()) if (MO->isImplicit())
report("Explicit operand marked as implicit", MO, MONum); report("Explicit operand marked as implicit", MO, MONum);
} }
@ -706,7 +707,6 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Check register classes. // Check register classes.
if (MONum < TI.getNumOperands() && !MO->isImplicit()) { if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
const TargetOperandInfo &TOI = TI.OpInfo[MONum];
unsigned SubIdx = MO->getSubReg(); unsigned SubIdx = MO->getSubReg();
if (TargetRegisterInfo::isPhysicalRegister(Reg)) { if (TargetRegisterInfo::isPhysicalRegister(Reg)) {