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https://github.com/RPCS3/llvm-mirror.git
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[SVE] Change definition of reduction ISD nodes to have an SVE vector result type.
The current nodes, AArch64::SMAXV_PRED for example, are defined to return a NEON vector result. This is incorrect because they modify the complete SVE register and are thus changed to represent such. This patch also adds nodes for UADDV_PRED and SADDV_PRED, which unifies the handling of all SVE reductions. NOTE: Floating-point reductions are already implemented correctly, so this patch is essentially making everything consistent with those. Differential Revision: https://reviews.llvm.org/D87843
This commit is contained in:
Paul Walker
parent
6eee9eb46a
commit
37b56bbc5e
@ -116,6 +116,27 @@ EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
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/// Value type used for condition codes.
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static const MVT MVT_CC = MVT::i32;
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static inline EVT getPackedSVEVectorVT(EVT VT) {
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switch (VT.getSimpleVT().SimpleTy) {
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default:
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llvm_unreachable("unexpected element type for vector");
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case MVT::i8:
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return MVT::nxv16i8;
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case MVT::i16:
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return MVT::nxv8i16;
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case MVT::i32:
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return MVT::nxv4i32;
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case MVT::i64:
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return MVT::nxv2i64;
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case MVT::f16:
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return MVT::nxv8f16;
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case MVT::f32:
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return MVT::nxv4f32;
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case MVT::f64:
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return MVT::nxv2f64;
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}
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}
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/// Returns true if VT's elements occupy the lowest bit positions of its
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/// associated register class without any intervening space.
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///
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@ -1587,6 +1608,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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MAKE_CASE(AArch64ISD::UMINV)
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MAKE_CASE(AArch64ISD::SMAXV)
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MAKE_CASE(AArch64ISD::UMAXV)
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MAKE_CASE(AArch64ISD::SADDV_PRED)
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MAKE_CASE(AArch64ISD::UADDV_PRED)
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MAKE_CASE(AArch64ISD::SMAXV_PRED)
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MAKE_CASE(AArch64ISD::UMAXV_PRED)
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MAKE_CASE(AArch64ISD::SMINV_PRED)
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@ -12221,34 +12244,6 @@ static SDValue combineAcrossLanesIntrinsic(unsigned Opc, SDNode *N,
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DAG.getConstant(0, dl, MVT::i64));
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}
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static SDValue LowerSVEIntReduction(SDNode *N, unsigned Opc,
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SelectionDAG &DAG) {
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SDLoc dl(N);
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LLVMContext &Ctx = *DAG.getContext();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT VT = N->getValueType(0);
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SDValue Pred = N->getOperand(1);
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SDValue Data = N->getOperand(2);
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EVT DataVT = Data.getValueType();
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if (DataVT.getVectorElementType().isScalarInteger() &&
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(VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)) {
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if (!TLI.isTypeLegal(DataVT))
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return SDValue();
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EVT OutputVT = EVT::getVectorVT(Ctx, VT,
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AArch64::NeonBitsPerVector / VT.getSizeInBits());
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SDValue Reduce = DAG.getNode(Opc, dl, OutputVT, Pred, Data);
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SDValue Zero = DAG.getConstant(0, dl, MVT::i64);
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SDValue Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Reduce, Zero);
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return Result;
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}
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return SDValue();
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}
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static SDValue LowerSVEIntrinsicIndex(SDNode *N, SelectionDAG &DAG) {
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SDLoc DL(N);
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SDValue Op1 = N->getOperand(1);
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@ -12392,6 +12387,25 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
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return DAG.getZExtOrTrunc(Res, DL, VT);
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}
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static SDValue combineSVEReductionInt(SDNode *N, unsigned Opc,
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SelectionDAG &DAG) {
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SDLoc DL(N);
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SDValue Pred = N->getOperand(1);
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SDValue VecToReduce = N->getOperand(2);
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// NOTE: The integer reduction's result type is not always linked to the
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// operand's element type so we construct it from the intrinsic's result type.
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EVT ReduceVT = getPackedSVEVectorVT(N->getValueType(0));
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SDValue Reduce = DAG.getNode(Opc, DL, ReduceVT, Pred, VecToReduce);
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// SVE reductions set the whole vector register with the first element
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// containing the reduction result, which we'll now extract.
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SDValue Zero = DAG.getConstant(0, DL, MVT::i64);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0), Reduce,
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Zero);
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}
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static SDValue combineSVEReductionFP(SDNode *N, unsigned Opc,
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SelectionDAG &DAG) {
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SDLoc DL(N);
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@ -12505,20 +12519,28 @@ static SDValue performIntrinsicCombine(SDNode *N,
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case Intrinsic::aarch64_crc32h:
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case Intrinsic::aarch64_crc32ch:
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return tryCombineCRC32(0xffff, N, DAG);
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case Intrinsic::aarch64_sve_saddv:
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// There is no i64 version of SADDV because the sign is irrelevant.
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if (N->getOperand(2)->getValueType(0).getVectorElementType() == MVT::i64)
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return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG);
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else
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return combineSVEReductionInt(N, AArch64ISD::SADDV_PRED, DAG);
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case Intrinsic::aarch64_sve_uaddv:
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return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG);
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case Intrinsic::aarch64_sve_smaxv:
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return LowerSVEIntReduction(N, AArch64ISD::SMAXV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::SMAXV_PRED, DAG);
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case Intrinsic::aarch64_sve_umaxv:
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return LowerSVEIntReduction(N, AArch64ISD::UMAXV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG);
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case Intrinsic::aarch64_sve_sminv:
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return LowerSVEIntReduction(N, AArch64ISD::SMINV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG);
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case Intrinsic::aarch64_sve_uminv:
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return LowerSVEIntReduction(N, AArch64ISD::UMINV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::UMINV_PRED, DAG);
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case Intrinsic::aarch64_sve_orv:
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return LowerSVEIntReduction(N, AArch64ISD::ORV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::ORV_PRED, DAG);
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case Intrinsic::aarch64_sve_eorv:
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return LowerSVEIntReduction(N, AArch64ISD::EORV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::EORV_PRED, DAG);
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case Intrinsic::aarch64_sve_andv:
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return LowerSVEIntReduction(N, AArch64ISD::ANDV_PRED, DAG);
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return combineSVEReductionInt(N, AArch64ISD::ANDV_PRED, DAG);
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case Intrinsic::aarch64_sve_index:
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return LowerSVEIntrinsicIndex(N, DAG);
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case Intrinsic::aarch64_sve_dup:
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@ -226,6 +226,8 @@ enum NodeType : unsigned {
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SMAXV,
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UMAXV,
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SADDV_PRED,
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UADDV_PRED,
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SMAXV_PRED,
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UMAXV_PRED,
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SMINV_PRED,
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@ -152,6 +152,8 @@ def AArch64fmaxv_p : SDNode<"AArch64ISD::FMAXV_PRED", SDT_AArch64Reduce>;
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def AArch64fmaxnmv_p : SDNode<"AArch64ISD::FMAXNMV_PRED", SDT_AArch64Reduce>;
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def AArch64fminv_p : SDNode<"AArch64ISD::FMINV_PRED", SDT_AArch64Reduce>;
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def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>;
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def AArch64saddv_p : SDNode<"AArch64ISD::SADDV_PRED", SDT_AArch64Reduce>;
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def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>;
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def AArch64smaxv_p : SDNode<"AArch64ISD::SMAXV_PRED", SDT_AArch64Reduce>;
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def AArch64umaxv_p : SDNode<"AArch64ISD::UMAXV_PRED", SDT_AArch64Reduce>;
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def AArch64sminv_p : SDNode<"AArch64ISD::SMINV_PRED", SDT_AArch64Reduce>;
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@ -307,8 +309,8 @@ let Predicates = [HasSVE] in {
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defm MLS_ZPmZZ : sve_int_mlas_vvv_pred<0b1, "mls", int_aarch64_sve_mls, sub, AArch64mul_p_oneuse>;
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// SVE predicated integer reductions.
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defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", int_aarch64_sve_saddv>;
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defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv", int_aarch64_sve_uaddv, int_aarch64_sve_saddv>;
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defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", AArch64saddv_p>;
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defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv", AArch64uaddv_p>;
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defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv", AArch64smaxv_p>;
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defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv", AArch64umaxv_p>;
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defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv", AArch64sminv_p>;
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@ -348,11 +348,6 @@ class SVE_2_Op_Pred_All_Active<ValueType vtd, SDPatternOperator op,
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: Pat<(vtd (op (pt (AArch64ptrue 31)), vt1:$Op1, vt2:$Op2)),
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(inst $Op1, $Op2)>;
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class SVE_2_Op_Pat_Reduce_To_Neon<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, Instruction inst, SubRegIndex sub>
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: Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
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(INSERT_SUBREG (vtd (IMPLICIT_DEF)), (inst $Op1, $Op2), sub)>;
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class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, ValueType vt3, Instruction inst>
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: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
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@ -4535,7 +4530,6 @@ multiclass sve_fp_fast_red<bits<3> opc, string asm, SDPatternOperator op> {
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def : SVE_2_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Accumulating Reduction Group
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//===----------------------------------------------------------------------===//
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@ -7173,8 +7167,8 @@ multiclass sve_int_bin_cons_misc_0_c_fexpa<string asm, SDPatternOperator op> {
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//===----------------------------------------------------------------------===//
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class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
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ZPRRegOp zprty, RegisterClass regtype>
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: I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
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ZPRRegOp zprty, FPRasZPROperand dstOpType>
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: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
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asm, "\t$Vd, $Pg, $Zn",
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"",
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[]>, Sched<[]> {
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@ -7192,51 +7186,54 @@ class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
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let Inst{4-0} = Vd;
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}
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multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
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def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
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def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
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multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm,
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SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64asZPR>;
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def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64asZPR>;
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def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64asZPR>;
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def : SVE_2_Op_Pat<i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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}
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multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm, SDPatternOperator op, SDPatternOperator opSaddv> {
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def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
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def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
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def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
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def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>;
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multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm,
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SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64asZPR>;
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def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64asZPR>;
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def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64asZPR>;
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def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64asZPR>;
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def : SVE_2_Op_Pat<i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
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def : SVE_2_Op_Pat<i64, opSaddv, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_reduce_1<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>;
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def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>;
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def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>;
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def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>;
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multiclass sve_int_reduce_1<bits<3> opc, string asm,
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SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8asZPR>;
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def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16asZPR>;
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def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32asZPR>;
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def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64asZPR>;
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def : SVE_2_Op_Pat_Reduce_To_Neon<v16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B), bsub>;
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def : SVE_2_Op_Pat_Reduce_To_Neon<v8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H), hsub>;
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def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
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def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
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def : SVE_2_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_reduce_2<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>;
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def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>;
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def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>;
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def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
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multiclass sve_int_reduce_2<bits<3> opc, string asm,
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SDPatternOperator op> {
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def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8asZPR>;
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def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16asZPR>;
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def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32asZPR>;
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||||
def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64asZPR>;
|
||||
|
||||
def : SVE_2_Op_Pat_Reduce_To_Neon<v16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B), bsub>;
|
||||
def : SVE_2_Op_Pat_Reduce_To_Neon<v8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H), hsub>;
|
||||
def : SVE_2_Op_Pat_Reduce_To_Neon<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S), ssub>;
|
||||
def : SVE_2_Op_Pat_Reduce_To_Neon<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D), dsub>;
|
||||
def : SVE_2_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
|
||||
def : SVE_2_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
|
||||
def : SVE_2_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
|
||||
def : SVE_2_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
|
||||
}
|
||||
|
||||
class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm,
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
|
||||
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
|
||||
|
||||
@ -6,9 +7,10 @@
|
||||
|
||||
define i64 @saddv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: saddv_i8:
|
||||
; CHECK: saddv d[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddv d0, p0, z0.b
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i64 %out
|
||||
@ -16,9 +18,10 @@ define i64 @saddv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i64 @saddv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: saddv_i16:
|
||||
; CHECK: saddv d[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddv d0, p0, z0.h
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.saddv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i64 %out
|
||||
@ -27,19 +30,21 @@ define i64 @saddv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i64 @saddv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: saddv_i32:
|
||||
; CHECK: saddv d[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: saddv d0, p0, z0.s
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.saddv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i64 %out
|
||||
}
|
||||
|
||||
define i64 @saddv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: saddv_i64
|
||||
; CHECK: uaddv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-LABEL: saddv_i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -47,9 +52,10 @@ define i64 @saddv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i64 @uaddv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: uaddv_i8:
|
||||
; CHECK: uaddv d[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddv d0, p0, z0.b
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i64 %out
|
||||
@ -57,9 +63,10 @@ define i64 @uaddv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i64 @uaddv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: uaddv_i16:
|
||||
; CHECK: uaddv d[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddv d0, p0, z0.h
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i64 %out
|
||||
@ -68,9 +75,10 @@ define i64 @uaddv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i64 @uaddv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: uaddv_i32:
|
||||
; CHECK: uaddv d[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddv d0, p0, z0.s
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.uaddv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i64 %out
|
||||
@ -78,9 +86,10 @@ define i64 @uaddv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @uaddv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: uaddv_i64:
|
||||
; CHECK: uaddv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uaddv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.uaddv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -88,9 +97,10 @@ define i64 @uaddv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @smaxv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: smaxv_i8:
|
||||
; CHECK: smaxv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smaxv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.smaxv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -98,9 +108,10 @@ define i8 @smaxv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @smaxv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: smaxv_i16:
|
||||
; CHECK: smaxv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smaxv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.smaxv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -108,9 +119,10 @@ define i16 @smaxv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @smaxv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: smaxv_i32:
|
||||
; CHECK: smaxv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smaxv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.smaxv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -118,9 +130,10 @@ define i32 @smaxv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @smaxv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: smaxv_i64:
|
||||
; CHECK: smaxv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: smaxv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -128,9 +141,10 @@ define i64 @smaxv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @umaxv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: umaxv_i8:
|
||||
; CHECK: umaxv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umaxv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -138,9 +152,10 @@ define i8 @umaxv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @umaxv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: umaxv_i16:
|
||||
; CHECK: umaxv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umaxv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.umaxv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -148,9 +163,10 @@ define i16 @umaxv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @umaxv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: umaxv_i32:
|
||||
; CHECK: umaxv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umaxv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.umaxv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -158,9 +174,10 @@ define i32 @umaxv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @umaxv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: umaxv_i64:
|
||||
; CHECK: umaxv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: umaxv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.umaxv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -168,9 +185,10 @@ define i64 @umaxv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @sminv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: sminv_i8:
|
||||
; CHECK: sminv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sminv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.sminv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -178,9 +196,10 @@ define i8 @sminv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @sminv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: sminv_i16:
|
||||
; CHECK: sminv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sminv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.sminv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -188,9 +207,10 @@ define i16 @sminv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @sminv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: sminv_i32:
|
||||
; CHECK: sminv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sminv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -198,9 +218,10 @@ define i32 @sminv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @sminv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: sminv_i64:
|
||||
; CHECK: sminv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: sminv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.sminv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -208,9 +229,10 @@ define i64 @sminv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @uminv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: uminv_i8:
|
||||
; CHECK: uminv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uminv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.uminv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -218,9 +240,10 @@ define i8 @uminv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @uminv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: uminv_i16:
|
||||
; CHECK: uminv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uminv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.uminv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -228,9 +251,10 @@ define i16 @uminv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @uminv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: uminv_i32:
|
||||
; CHECK: uminv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uminv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.uminv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -238,9 +262,10 @@ define i32 @uminv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @uminv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: uminv_i64:
|
||||
; CHECK: uminv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: uminv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -248,9 +273,10 @@ define i64 @uminv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @orv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: orv_i8:
|
||||
; CHECK: orv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: orv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -258,9 +284,10 @@ define i8 @orv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @orv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: orv_i16:
|
||||
; CHECK: orv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: orv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.orv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -268,9 +295,10 @@ define i16 @orv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @orv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: orv_i32:
|
||||
; CHECK: orv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: orv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -278,9 +306,10 @@ define i32 @orv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @orv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: orv_i64:
|
||||
; CHECK: orv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: orv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.orv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -288,9 +317,10 @@ define i64 @orv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @eorv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: eorv_i8:
|
||||
; CHECK: eorv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eorv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.eorv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -298,9 +328,10 @@ define i8 @eorv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @eorv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: eorv_i16:
|
||||
; CHECK: eorv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eorv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -308,9 +339,10 @@ define i16 @eorv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @eorv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: eorv_i32:
|
||||
; CHECK: eorv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eorv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -318,9 +350,10 @@ define i32 @eorv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @eorv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: eorv_i64:
|
||||
; CHECK: eorv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: eorv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.eorv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
@ -328,9 +361,10 @@ define i64 @eorv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
|
||||
define i8 @andv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
; CHECK-LABEL: andv_i8:
|
||||
; CHECK: andv b[[REDUCE:[0-9]+]], p0, z0.b
|
||||
; CHECK: umov w0, v[[REDUCE]].b[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: andv b0, p0, z0.b
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a)
|
||||
ret i8 %out
|
||||
@ -338,9 +372,10 @@ define i8 @andv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
|
||||
|
||||
define i16 @andv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
; CHECK-LABEL: andv_i16:
|
||||
; CHECK: andv h[[REDUCE:[0-9]+]], p0, z0.h
|
||||
; CHECK: umov w0, v[[REDUCE]].h[0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: andv h0, p0, z0.h
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i16 @llvm.aarch64.sve.andv.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a)
|
||||
ret i16 %out
|
||||
@ -348,9 +383,10 @@ define i16 @andv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
|
||||
|
||||
define i32 @andv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: andv_i32:
|
||||
; CHECK: andv s[[REDUCE:[0-9]+]], p0, z0.s
|
||||
; CHECK: fmov w0, s[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: andv s0, p0, z0.s
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i32 @llvm.aarch64.sve.andv.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a)
|
||||
ret i32 %out
|
||||
@ -358,9 +394,10 @@ define i32 @andv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {
|
||||
|
||||
define i64 @andv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {
|
||||
; CHECK-LABEL: andv_i64:
|
||||
; CHECK: andv d[[REDUCE:[0-9]+]], p0, z0.d
|
||||
; CHECK: fmov x0, d[[REDUCE]]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: andv d0, p0, z0.d
|
||||
; CHECK-NEXT: fmov x0, d0
|
||||
; CHECK-NEXT: ret
|
||||
%out = call i64 @llvm.aarch64.sve.andv.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a)
|
||||
ret i64 %out
|
||||
|
||||
Loading…
Reference in New Issue
Block a user