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https://github.com/RPCS3/llvm-mirror.git
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[VE] Clean SDNodeXForm stuff
Summary: Gather definitions of SDNodeXForm and change them to call C functions instead of copying C expressions in td files. Doing this solved some bugs in mimm detections. Differential Revision: https://reviews.llvm.org/D81132
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
42f802871d
commit
37d0f82ab6
@ -126,6 +126,34 @@ inline static const char *VERDToString(VERD::RoundingMode R) {
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}
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}
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// MImm - Special immediate value of sequential bit stream of 0 or 1.
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// See VEInstrInfo.td for details.
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inline static bool isMImmVal(uint64_t Val) {
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if (Val == 0) {
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// (0)1 is 0
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return true;
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}
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if (isMask_64(Val)) {
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// (m)0 patterns
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return true;
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}
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// (m)1 patterns
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return (Val & (1UL << 63)) && isShiftedMask_64(Val);
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}
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inline static bool isMImm32Val(uint32_t Val) {
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if (Val == 0) {
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// (0)1 is 0
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return true;
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}
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if (isMask_32(Val)) {
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// (m)0 patterns
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return true;
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}
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// (m)1 patterns
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return (Val & (1 << 31)) && isShiftedMask_32(Val);
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}
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inline unsigned M0(unsigned Val) { return Val + 64; }
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inline unsigned M1(unsigned Val) { return Val; }
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@ -23,6 +23,105 @@ using namespace llvm;
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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/// Convert a DAG integer condition code to a VE ICC condition.
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inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unknown integer condition code!");
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case ISD::SETEQ:
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return VECC::CC_IEQ;
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case ISD::SETNE:
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return VECC::CC_INE;
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case ISD::SETLT:
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return VECC::CC_IL;
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case ISD::SETGT:
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return VECC::CC_IG;
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case ISD::SETLE:
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return VECC::CC_ILE;
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case ISD::SETGE:
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return VECC::CC_IGE;
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case ISD::SETULT:
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return VECC::CC_IL;
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case ISD::SETULE:
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return VECC::CC_ILE;
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case ISD::SETUGT:
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return VECC::CC_IG;
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case ISD::SETUGE:
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return VECC::CC_IGE;
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}
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}
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/// Convert a DAG floating point condition code to a VE FCC condition.
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inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unknown fp condition code!");
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case ISD::SETFALSE:
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return VECC::CC_AF;
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case ISD::SETEQ:
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case ISD::SETOEQ:
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return VECC::CC_EQ;
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case ISD::SETNE:
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case ISD::SETONE:
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return VECC::CC_NE;
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case ISD::SETLT:
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case ISD::SETOLT:
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return VECC::CC_L;
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case ISD::SETGT:
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case ISD::SETOGT:
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return VECC::CC_G;
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case ISD::SETLE:
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case ISD::SETOLE:
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return VECC::CC_LE;
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case ISD::SETGE:
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case ISD::SETOGE:
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return VECC::CC_GE;
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case ISD::SETO:
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return VECC::CC_NUM;
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case ISD::SETUO:
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return VECC::CC_NAN;
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case ISD::SETUEQ:
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return VECC::CC_EQNAN;
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case ISD::SETUNE:
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return VECC::CC_NENAN;
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case ISD::SETULT:
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return VECC::CC_LNAN;
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case ISD::SETUGT:
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return VECC::CC_GNAN;
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case ISD::SETULE:
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return VECC::CC_LENAN;
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case ISD::SETUGE:
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return VECC::CC_GENAN;
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case ISD::SETTRUE:
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return VECC::CC_AT;
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}
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}
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/// getImmVal - get immediate representation of integer value
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inline static uint64_t getImmVal(const ConstantSDNode *N) {
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return N->getSExtValue();
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}
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/// getFpImmVal - get immediate representation of floating point value
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inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
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const APInt &Imm = N->getValueAPF().bitcastToAPInt();
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uint64_t Val = Imm.getZExtValue();
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if (Imm.getBitWidth() == 32) {
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// Immediate value of float place places at higher bits on VE.
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Val <<= 32;
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}
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return Val;
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}
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/// convMImmVal - Convert a mimm integer immediate value to target immediate.
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inline static uint64_t convMImmVal(uint64_t Val) {
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if (Val == 0)
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return 0; // (0)1
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if (Val & (1UL << 63))
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return countLeadingOnes(Val); // (m)1
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return countLeadingZeros(Val) | 0x40; // (m)0
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}
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//===--------------------------------------------------------------------===//
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/// VEDAGToDAGISel - VE specific code to select VE machine
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/// instructions for SelectionDAG operations.
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@ -16,6 +16,85 @@
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include "VEInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Helper functions to retrieve target constants.
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//
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// VE instructions have a space to hold following immediates
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// $sy has 7 bits to represent simm7, uimm7, simm7fp, or uimm7fp.
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// $sz also has 7 bits to represent mimm or mimmfp.
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// $disp has 32 bits to represent simm32.
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//
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// The mimm is a special immediate value of sequential bit stream of 0 or 1.
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// `(m)0`: Represents 0 sequence then 1 sequence like 0b00...0011...11,
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// where `m` is equal to the number of leading zeros.
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// `(m)1`: Represents 1 sequence then 0 sequence like 0b11...1100...00,
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// where `m` is equal to the number of leading ones.
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// Each bit of mimm's 7 bits is used like below:
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// bit 6 : If `(m)0`, this bit is 1. Otherwise, this bit is 0.
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// bit 5-0: Represents the m (0-63).
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// Use `!add(m, 64)` to generates an immediate value in pattern matchings.
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//
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// The floating point immediate value is not something like compacted value.
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// It is simple integer representation, so it works rarely.
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// e.g. 0.0 (0x00000000) or -2.0 (0xC0000000=(2)1).
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//===----------------------------------------------------------------------===//
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def LO7 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
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SDLoc(N), MVT::i32);
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}]>;
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def MIMM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(convMImmVal(getImmVal(N)),
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SDLoc(N), MVT::i32);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(Lo_32(N->getZExtValue()),
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SDLoc(N), MVT::i32);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
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SDLoc(N), MVT::i32);
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}]>;
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def LO7FP : SDNodeXForm<fpimm, [{
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uint64_t Val = getFpImmVal(N);
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return CurDAG->getTargetConstant(SignExtend32(Val, 7), SDLoc(N), MVT::i32);
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}]>;
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def MIMMFP : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(convMImmVal(getFpImmVal(N)),
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SDLoc(N), MVT::i32);
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}]>;
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def LOFP32 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(Lo_32(getFpImmVal(N) & 0xffffffff),
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SDLoc(N), MVT::i32);
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}]>;
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def HIFP32 : SDNodeXForm<fpimm, [{
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return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32);
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}]>;
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def icond2cc : SDNodeXForm<cond, [{
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VECC::CondCode VECC = intCondCode2Icc(N->get());
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return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);
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}]>;
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def icond2ccSwap : SDNodeXForm<cond, [{
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ISD::CondCode CC = getSetCCSwappedOperands(N->get());
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VECC::CondCode VECC = intCondCode2Icc(CC);
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return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);
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}]>;
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def fcond2cc : SDNodeXForm<cond, [{
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VECC::CondCode VECC = fpCondCode2Fcc(N->get());
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return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);
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}]>;
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def fcond2ccSwap : SDNodeXForm<cond, [{
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ISD::CondCode CC = getSetCCSwappedOperands(N->get());
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VECC::CondCode VECC = fpCondCode2Fcc(CC);
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return CurDAG->getTargetConstant(VECC, SDLoc(N), MVT::i32);
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}]>;
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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@ -37,90 +116,48 @@ def uimm7 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<7>(N->getZExtValue()); }]>;
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// simm7 - Generic immediate value.
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def LO7 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(SignExtend32(N->getSExtValue(), 7),
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SDLoc(N), MVT::i32);
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}]>;
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def simm7 : Operand<i32>, PatLeaf<(imm), [{
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return isInt<7>(N->getSExtValue()); }], LO7> {
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let DecoderMethod = "DecodeSIMM7";
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}
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// mimm - Special immediate value of sequential bit stream of 0 or 1.
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// `(m)0`: Represents 0b00...0011...11 pattern where the number of leading
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// zeros equal to m.
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// `(m)1`: Represents 0b11...1100...00 pattern where the number of leading
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// ones equal to m.
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// The immediate value of mimm operands:
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// bit 6 : If `(m)0`, 1. Otherwise, 0.
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// bit 5-0: Represents 0-63.
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// Use `!add(m, 64)` to generates an immediate value in pattern matching.
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def MIMM : SDNodeXForm<imm, [{
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uint64_t Val = N->getZExtValue();
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if (isMask_64(Val))
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Val = countLeadingZeros(Val) | 0x40;
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else
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Val = countLeadingOnes(Val);
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return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
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}]>;
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def mimm : Operand<i32>, PatLeaf<(imm), [{
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return isMask_64(N->getZExtValue()) ||
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((N->getZExtValue() & (1UL << 63)) &&
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isShiftedMask_64(N->getZExtValue())); }], MIMM> {
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return isMImmVal(getImmVal(N)); }], MIMM> {
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let PrintMethod = "printMImmOperand";
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}
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// simm7fp - Generic fp immediate value.
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def LO7FP : SDNodeXForm<fpimm, [{
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// Get a integer immediate from fpimm
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const APInt& imm = N->getValueAPF().bitcastToAPInt();
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uint64_t val = imm.getSExtValue();
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if (imm.getBitWidth() == 32)
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val <<= 32; // Immediate value of float place at higher bits on VE.
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return CurDAG->getTargetConstant(SignExtend32(val, 7), SDLoc(N), MVT::i32);
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}]>;
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def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
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const APInt& imm = N->getValueAPF().bitcastToAPInt();
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uint64_t val = imm.getSExtValue();
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if (imm.getBitWidth() == 32)
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val <<= 32; // Immediate value of float place at higher bits on VE.
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return isInt<7>(val);
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return isInt<7>(getFpImmVal(N));
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}], LO7FP> {
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let DecoderMethod = "DecodeSIMM7";
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}
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// mimm - Special fp immediate value of sequential bit stream of 0 or 1.
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def MIMMFP : SDNodeXForm<fpimm, [{
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const APInt& Imm = N->getValueAPF().bitcastToAPInt();
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uint64_t Val = Imm.getSExtValue();
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bool M0Flag = isMask_64(Val);
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if (Imm.getBitWidth() == 32)
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Val <<= 32; // Immediate value of float place at higher bits on VE.
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if (M0Flag) {
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// bit 6 : If `(m)0`, 1. Otherwise, 0.
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Val = countLeadingZeros(Val) | 0x40;
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} else
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Val = countLeadingOnes(Val);
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return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
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}]>;
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// mimmfp - Special fp immediate value of sequential bit stream of 0 or 1.
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def mimmfp : Operand<i32>, PatLeaf<(fpimm), [{
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const APInt& Imm = N->getValueAPF().bitcastToAPInt();
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uint64_t Val = Imm.getSExtValue();
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return isMask_64(Val) ||
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((Val & (1UL << 63)) && isShiftedMask_64(Val)); }], MIMMFP> {
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return isMImmVal(getFpImmVal(N)); }], MIMMFP> {
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let PrintMethod = "printMImmOperand";
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}
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// mimmfp32 - 32 bit width mimmfp
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// Float value places at higher bits, so ignore lower 32 bits.
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def mimmfp32 : Operand<i32>, PatLeaf<(fpimm), [{
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return isMImm32Val(getFpImmVal(N) >> 32); }], MIMMFP> {
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let PrintMethod = "printMImmOperand";
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}
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// other generic patterns to use in pattern matchings
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def simm32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
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def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
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def lomsbzero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0x80000000)
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== 0; }]>;
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def lozero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff)
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== 0; }]>;
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def fplomsbzero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt()
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.getZExtValue() & 0x80000000) == 0; }]>;
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def fplozero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt()
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.getZExtValue() & 0xffffffff) == 0; }]>;
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def fplomsbzero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0x80000000)
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== 0; }]>;
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def fplozero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0xffffffff)
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== 0; }]>;
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def CCSIOp : PatLeaf<(cond), [{
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switch (N->get()) {
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@ -142,127 +179,6 @@ def CCUIOp : PatLeaf<(cond), [{
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}
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}]>;
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def LOFP32 : SDNodeXForm<fpimm, [{
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// Get a integer immediate from fpimm
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const APInt& imm = N->getValueAPF().bitcastToAPInt();
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return CurDAG->getTargetConstant(Lo_32(imm.getZExtValue() & 0xffffffff),
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SDLoc(N), MVT::i64);
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}]>;
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def HIFP32 : SDNodeXForm<fpimm, [{
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// Get a integer immediate from fpimm
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const APInt& imm = N->getValueAPF().bitcastToAPInt();
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return CurDAG->getTargetConstant(Hi_32(imm.getZExtValue()),
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SDLoc(N), MVT::i64);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(Lo_32(N->getZExtValue()),
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SDLoc(N), MVT::i64);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
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SDLoc(N), MVT::i32);
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}]>;
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def icond2cc : SDNodeXForm<cond, [{
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VECC::CondCode cc;
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switch (N->get()) {
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default: llvm_unreachable("Unknown integer condition code!");
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case ISD::SETEQ: cc = VECC::CC_IEQ; break;
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case ISD::SETNE: cc = VECC::CC_INE; break;
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case ISD::SETLT: cc = VECC::CC_IL; break;
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case ISD::SETGT: cc = VECC::CC_IG; break;
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case ISD::SETLE: cc = VECC::CC_ILE; break;
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case ISD::SETGE: cc = VECC::CC_IGE; break;
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case ISD::SETULT: cc = VECC::CC_IL; break;
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case ISD::SETULE: cc = VECC::CC_ILE; break;
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case ISD::SETUGT: cc = VECC::CC_IG; break;
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case ISD::SETUGE: cc = VECC::CC_IGE; break;
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}
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return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
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}]>;
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def icond2ccSwap : SDNodeXForm<cond, [{
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VECC::CondCode cc;
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switch (N->get()) {
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default: llvm_unreachable("Unknown integer condition code!");
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case ISD::SETEQ: cc = VECC::CC_IEQ; break;
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case ISD::SETNE: cc = VECC::CC_INE; break;
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case ISD::SETLT: cc = VECC::CC_IG; break;
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case ISD::SETGT: cc = VECC::CC_IL; break;
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case ISD::SETLE: cc = VECC::CC_IGE; break;
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case ISD::SETGE: cc = VECC::CC_ILE; break;
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case ISD::SETULT: cc = VECC::CC_IG; break;
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case ISD::SETULE: cc = VECC::CC_IGE; break;
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case ISD::SETUGT: cc = VECC::CC_IL; break;
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case ISD::SETUGE: cc = VECC::CC_ILE; break;
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}
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return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
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}]>;
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def fcond2cc : SDNodeXForm<cond, [{
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VECC::CondCode cc;
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switch (N->get()) {
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default: llvm_unreachable("Unknown float condition code!");
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case ISD::SETFALSE: cc = VECC::CC_AF; break;
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case ISD::SETEQ:
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case ISD::SETOEQ: cc = VECC::CC_EQ; break;
|
||||
case ISD::SETNE:
|
||||
case ISD::SETONE: cc = VECC::CC_NE; break;
|
||||
case ISD::SETLT:
|
||||
case ISD::SETOLT: cc = VECC::CC_L; break;
|
||||
case ISD::SETGT:
|
||||
case ISD::SETOGT: cc = VECC::CC_G; break;
|
||||
case ISD::SETLE:
|
||||
case ISD::SETOLE: cc = VECC::CC_LE; break;
|
||||
case ISD::SETGE:
|
||||
case ISD::SETOGE: cc = VECC::CC_GE; break;
|
||||
case ISD::SETO: cc = VECC::CC_NUM; break;
|
||||
case ISD::SETUO: cc = VECC::CC_NAN; break;
|
||||
case ISD::SETUEQ: cc = VECC::CC_EQNAN; break;
|
||||
case ISD::SETUNE: cc = VECC::CC_NENAN; break;
|
||||
case ISD::SETULT: cc = VECC::CC_LNAN; break;
|
||||
case ISD::SETUGT: cc = VECC::CC_GNAN; break;
|
||||
case ISD::SETULE: cc = VECC::CC_LENAN; break;
|
||||
case ISD::SETUGE: cc = VECC::CC_GENAN; break;
|
||||
case ISD::SETTRUE: cc = VECC::CC_AT; break;
|
||||
}
|
||||
return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
|
||||
}]>;
|
||||
|
||||
def fcond2ccSwap : SDNodeXForm<cond, [{
|
||||
VECC::CondCode cc;
|
||||
switch (N->get()) {
|
||||
default: llvm_unreachable("Unknown float condition code!");
|
||||
case ISD::SETFALSE: cc = VECC::CC_AF; break;
|
||||
case ISD::SETEQ:
|
||||
case ISD::SETOEQ: cc = VECC::CC_EQ; break;
|
||||
case ISD::SETNE:
|
||||
case ISD::SETONE: cc = VECC::CC_NE; break;
|
||||
case ISD::SETLT:
|
||||
case ISD::SETOLT: cc = VECC::CC_G; break;
|
||||
case ISD::SETGT:
|
||||
case ISD::SETOGT: cc = VECC::CC_L; break;
|
||||
case ISD::SETLE:
|
||||
case ISD::SETOLE: cc = VECC::CC_GE; break;
|
||||
case ISD::SETGE:
|
||||
case ISD::SETOGE: cc = VECC::CC_LE; break;
|
||||
case ISD::SETO: cc = VECC::CC_NUM; break;
|
||||
case ISD::SETUO: cc = VECC::CC_NAN; break;
|
||||
case ISD::SETUEQ: cc = VECC::CC_EQNAN; break;
|
||||
case ISD::SETUNE: cc = VECC::CC_NENAN; break;
|
||||
case ISD::SETULT: cc = VECC::CC_GNAN; break;
|
||||
case ISD::SETUGT: cc = VECC::CC_LNAN; break;
|
||||
case ISD::SETULE: cc = VECC::CC_GENAN; break;
|
||||
case ISD::SETUGE: cc = VECC::CC_LENAN; break;
|
||||
case ISD::SETTRUE: cc = VECC::CC_AT; break;
|
||||
}
|
||||
return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
|
||||
}]>;
|
||||
|
||||
// Addressing modes.
|
||||
// SX-Aurora has following fields.
|
||||
// sz: register or 0
|
||||
@ -1013,30 +929,39 @@ def : Pat<(i32 (srl i32:$src, i32:$val)),
|
||||
|
||||
// Section 8.7.1 - FAD (Floating Add)
|
||||
defm FADDD : RRFm<"fadd.d", 0x4C, I64, f64, fadd>;
|
||||
let cx = 1 in defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd>;
|
||||
let cx = 1 in
|
||||
defm FADDS : RRFm<"fadd.s", 0x4C, F32, f32, fadd, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.2 - FSB (Floating Subtract)
|
||||
defm FSUBD : RRFm<"fsub.d", 0x5C, I64, f64, fsub>;
|
||||
let cx = 1 in defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub>;
|
||||
let cx = 1 in
|
||||
defm FSUBS : RRFm<"fsub.s", 0x5C, F32, f32, fsub, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.3 - FMP (Floating Multiply)
|
||||
defm FMULD : RRFm<"fmul.d", 0x4D, I64, f64, fmul>;
|
||||
let cx = 1 in defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul>;
|
||||
let cx = 1 in
|
||||
defm FMULS : RRFm<"fmul.s", 0x4D, F32, f32, fmul, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.4 - FDV (Floating Divide)
|
||||
defm FDIVD : RRFm<"fdiv.d", 0x5D, I64, f64, fdiv>;
|
||||
let cx = 1 in defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv>;
|
||||
let cx = 1 in
|
||||
defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.5 - FCP (Floating Compare)
|
||||
defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64>;
|
||||
let cx = 1 in defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32>;
|
||||
let cx = 1 in
|
||||
defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, null_frag, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.6 - CMS (Compare and Select Maximum/Minimum Single)
|
||||
// cx: double/float, cw: max/min
|
||||
defm FMAXD : RRFm<"fmax.d", 0x3E, I64, f64>;
|
||||
let cx = 1 in defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32>;
|
||||
let cw = 1 in defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64>;
|
||||
let cw = 1, cx = 1 in defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32>;
|
||||
let cw = 0, cx = 0 in
|
||||
defm FMAXD : RRFm<"fmax.d", 0x3E, I64, f64, fmaxnum>;
|
||||
let cw = 0, cx = 1 in
|
||||
defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;
|
||||
let cw = 1, cx = 0 in
|
||||
defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>;
|
||||
let cw = 1, cx = 1 in
|
||||
defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>;
|
||||
|
||||
// Section 8.7.7 - FAQ (Floating Add Quadruple)
|
||||
// Section 8.7.8 - FSQ (Floating Subtract Quadruple)
|
||||
@ -1161,7 +1086,7 @@ def : Pat<(i64 imm:$val),
|
||||
|
||||
// floating point
|
||||
def : Pat<(f32 fpimm:$val),
|
||||
(EXTRACT_SUBREG (LEASLzii 0, 0, (LOFP32 $val)), sub_f32)>;
|
||||
(EXTRACT_SUBREG (LEASLzii 0, 0, (HIFP32 $val)), sub_f32)>;
|
||||
def : Pat<(f64 fplozero:$val),
|
||||
(LEASLzii 0, 0, (HIFP32 $val))>;
|
||||
def : Pat<(f64 fplomsbzero:$val),
|
||||
|
||||
@ -159,8 +159,7 @@ define i64 @func21(i64 %0) {
|
||||
define i32 @func25(i32 %0) {
|
||||
; CHECK-LABEL: func25:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: lea %s1, -2147483648
|
||||
; CHECK-NEXT: xor %s0, %s0, %s1
|
||||
; CHECK-NEXT: xor %s0, %s0, (33)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%2 = xor i32 %0, -2147483648
|
||||
ret i32 %2
|
||||
|
||||
@ -63,7 +63,7 @@ define double @func8(double %a) {
|
||||
define float @fmuls_ir(float %a) {
|
||||
; CHECK-LABEL: fmuls_ir:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: fmul.s %s0, 0, %s0
|
||||
; CHECK-NEXT: fmul.s %s0, %s0, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%r = fmul float 0.e+00, %a
|
||||
ret float %r
|
||||
|
||||
@ -159,8 +159,7 @@ define i64 @func21(i64 %0, i64 %1) {
|
||||
define i32 @func25(i32 %0, i32 %1) {
|
||||
; CHECK-LABEL: func25:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: lea %s1, -2147483648
|
||||
; CHECK-NEXT: xor %s0, %s0, %s1
|
||||
; CHECK-NEXT: xor %s0, %s0, (33)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = xor i32 %0, -2147483648
|
||||
ret i32 %3
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user