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Only enable LiveRangeShrink for x86.

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Summary: Moving LiveRangeShrink to x86 as this pass is mostly useful for archtectures with great register pressure.

Reviewers: MatzeB, qcolombet

Reviewed By: qcolombet

Subscribers: jholewinski, jyknight, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33294

llvm-svn: 303292
This commit is contained in:
Dehao Chen 2017-05-17 20:18:13 +00:00
parent 0ece5089f7
commit 37da4a5e47
6 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/TargetPassConfig.cpp
View File

@ -623,9 +623,6 @@ void TargetPassConfig::addMachinePasses() {
addPass(&LocalStackSlotAllocationID, false);
}
if (getOptLevel() != CodeGenOpt::None)
addPass(&LiveRangeShrinkID);
// Run pre-ra passes.
addPreRegAlloc();

1
lib/Target/X86/X86TargetMachine.cpp
View File

@ -438,6 +438,7 @@ bool X86PassConfig::addPreISel() {
void X86PassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOpt::None) {
addPass(&LiveRangeShrinkID);
addPass(createX86FixupSetCC());
addPass(createX86OptimizeLEAs());
addPass(createX86CallFrameOptimization());

2
test/CodeGen/AArch64/arm64-ccmp.ll
View File

@ -378,11 +378,11 @@ define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
; CHECK-NEXT: cmp x0, #13
; CHECK-NOT: ccmp
; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
; CHECK-NEXT: cmp x2, #2
; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
; CHECK-NEXT: cmp x2, #4
; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
; CHECK-NEXT: cmp [[REG6]], #0

4
test/CodeGen/NVPTX/sched1.ll
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@ -6,10 +6,10 @@ define void @foo(i32* %a) {
; CHECK: .func foo
; CHECK: ld.u32
; CHECK-NEXT: ld.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: ld.u32
; CHECK-NEXT: ld.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: ld.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
%ptr0 = getelementptr i32, i32* %a, i32 0
%val0 = load i32, i32* %ptr0

6
test/CodeGen/NVPTX/sched2.ll
View File

@ -4,12 +4,12 @@ define void @foo(<2 x i32>* %a) {
; CHECK: .func foo
; CHECK: ld.v2.u32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: ld.v2.u32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
; CHECK-NEXT: add.s32
%ptr0 = getelementptr <2 x i32>, <2 x i32>* %a, i32 0

2
test/CodeGen/SPARC/LeonItinerariesUT.ll
View File

@ -28,8 +28,8 @@
; LEON3_4_ITIN-LABEL: f32_ops:
; LEON3_4_ITIN: ld
; LEON3_4_ITIN-NEXT: ld
; LEON3_4_ITIN-NEXT: fadds
; LEON3_4_ITIN-NEXT: ld
; LEON3_4_ITIN-NEXT: fadds
; LEON3_4_ITIN-NEXT: ld
; LEON3_4_ITIN-NEXT: fsubs
; LEON3_4_ITIN-NEXT: fmuls