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Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>

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llvm-svn: 118864
This commit is contained in:
Bruno Cardoso Lopes 2010-11-12 00:38:32 +00:00
parent 6f46d6f99f
commit 37f2439cbd
4 changed files with 21 additions and 3 deletions
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2
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@ -386,6 +386,8 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
/// Special Muls
case ISD::MUL:
if (Subtarget.isMips32())
break;
case ISD::MULHS:
case ISD::MULHU: {
SDValue MulOp1 = Node->getOperand(0);

3
lib/Target/Mips/MipsInstrInfo.td
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@ -62,6 +62,7 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
def HasSwap : Predicate<"Subtarget.hasSwap()">;
def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
def IsMips32 : Predicate<"Subtarget.isMips32()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@ -487,7 +488,7 @@ def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
// MUL is a assembly macro in the current used ISAs. In recent ISA's
// it is a real instruction.
//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions

4
lib/Target/Mips/MipsSubtarget.h
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@ -31,7 +31,7 @@ public:
protected:
enum MipsArchEnum {
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
};
// Mips architecture version
@ -100,7 +100,7 @@ public:
const std::string &CPU);
bool isMips1() const { return MipsArchVersion == Mips1; }
bool isMips32() const { return MipsArchVersion == Mips32; }
bool isMips32() const { return MipsArchVersion >= Mips32; }
bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
bool isLittle() const { return IsLittle; }

15
test/CodeGen/Mips/2010-11-09-Mul.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; CHECK: mul $2, $5, $4
define i32 @mul1(i32 %a, i32 %b) nounwind readnone {
entry:
%mul = mul i32 %b, %a
ret i32 %mul
}
; CHECK: mul $2, $5, $4
define i32 @mul2(i32 %a, i32 %b) nounwind readnone {
entry:
%mul = mul nsw i32 %b, %a
ret i32 %mul
}