1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 11:02:59 +02:00

Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W

bit should be set to 0 instead of 1.

llvm-svn: 97481
This commit is contained in:
Johnny Chen 2010-03-01 19:22:00 +00:00
parent 66fd0f6b4b
commit 37f3172799
2 changed files with 10 additions and 2 deletions

View File

@ -815,7 +815,7 @@ class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{6} = 0; // S bit
let Inst{7} = 1;
let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit
let Inst{21} = 0; // W bit
let Inst{24} = 0; // P bit
let Inst{27-25} = 0b000;
}

View File

@ -1260,7 +1260,7 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
"strd", "\t$src1, $src2, [$base], $offset",
"$base = $base_wb", []>;
// STRT and STRBT are for disassembly only.
// STRT, STRBT, and STRHT are for disassembly only.
def STRT : AI2stwpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
@ -1278,6 +1278,14 @@ def STRBT : AI2stbpo<(outs GPR:$base_wb),
let Inst{21} = 1; // overwrite
}
def STRHT: AI3sthpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset),
StMiscFrm, IIC_iStoreru,
"strht", "\t$src, [$base], $offset", "$base = $base_wb",
[/* For disassembly only; pattern left blank */]> {
let Inst{21} = 1; // overwrite
}
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
//