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[AMDGPU] gfx1010 VOPC implementation

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Differential Revision: https://reviews.llvm.org/D61208

llvm-svn: 359358
This commit is contained in:
Stanislav Mekhanoshin 2019-04-26 23:16:16 +00:00
parent 338f540e7b
commit 38215cf1a9
9 changed files with 681 additions and 349 deletions
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3
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -6003,7 +6003,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
skippedVcc = false;
}
if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 &&
if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 &&
Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 &&
Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) {
// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments
switch (BasicInstType) {

76
lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
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@ -393,16 +393,31 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
O << "_e64 ";
else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
O << "_dpp ";
else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
O << "_sdwa ";
else
O << "_e32 ";
if (OpNo == 0) {
if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
O << "_e64 ";
else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
O << "_dpp ";
else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
O << "_sdwa ";
else
O << "_e32 ";
}
printOperand(MI, OpNo, STI, O);
switch (MI->getOpcode()) {
default: break;
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
printDefaultVccOperand(1, STI, O);
break;
}
}
void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
@ -527,9 +542,25 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
}
}
void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
if (OpNo > 0)
O << ", ";
printRegOperand(AMDGPU::VCC, O, MRI);
if (OpNo == 0)
O << ", ";
}
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
printDefaultVccOperand(OpNo, STI, O);
if (OpNo >= MI->getNumOperands()) {
O << "/*Missing OP" << OpNo << "*/";
return;
@ -539,7 +570,6 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Op.isReg()) {
printRegOperand(Op.getReg(), O, MRI);
} else if (Op.isImm()) {
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
switch (Desc.OpInfo[OpNo].OperandType) {
case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_FP32:
@ -599,6 +629,22 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
} else {
O << "/*INV_OP*/";
}
switch (MI->getOpcode()) {
default: break;
case AMDGPU::V_CNDMASK_B32_e32_gfx10:
case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
case AMDGPU::V_CNDMASK_B32_e32_vi:
if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo, STI, O);
break;
}
}
void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
@ -646,6 +692,18 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
printOperand(MI, OpNo + 1, STI, O);
if (InputModifiers & SISrcMods::SEXT)
O << ')';
switch (MI->getOpcode()) {
default: break;
case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
printDefaultVccOperand(OpNo, STI, O);
break;
}
}
void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,

2
lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
View File

@ -149,6 +149,8 @@ private:
const MCSubtargetInfo &STI, raw_ostream &O);
void printMemOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printDefaultVccOperand(unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
template <unsigned N>

22
lib/Target/AMDGPU/SIInsertSkips.cpp
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@ -248,6 +248,10 @@ void SIInsertSkips::kill(MachineInstr &MI) {
llvm_unreachable("invalid ISD:SET cond code");
}
const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>();
if (ST.hasNoSdstCMPX())
Opcode = AMDGPU::getVCMPXNoSDstOp(Opcode);
assert(MI.getOperand(0).isReg());
if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
@ -257,13 +261,17 @@ void SIInsertSkips::kill(MachineInstr &MI) {
.add(MI.getOperand(1))
.add(MI.getOperand(0));
} else {
BuildMI(MBB, &MI, DL, TII->get(Opcode))
.addReg(AMDGPU::VCC, RegState::Define)
.addImm(0) // src0 modifiers
.add(MI.getOperand(1))
.addImm(0) // src1 modifiers
.add(MI.getOperand(0))
.addImm(0); // omod
auto I = BuildMI(MBB, &MI, DL, TII->get(Opcode));
if (!ST.hasNoSdstCMPX())
I.addReg(AMDGPU::VCC, RegState::Define);
I.addImm(0) // src0 modifiers
.add(MI.getOperand(1))
.addImm(0) // src1 modifiers
.add(MI.getOperand(0));
if (!ST.hasNoSdstCMPX())
I.addImm(0); // omod
}
break;
}

11
lib/Target/AMDGPU/SIInstrInfo.h
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@ -379,6 +379,14 @@ public:
return get(Opcode).TSFlags & SIInstrFlags::SOPP;
}
static bool isPacked(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
}
bool isPacked(uint16_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
}
static bool isVOP1(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
}
@ -1014,6 +1022,9 @@ namespace AMDGPU {
LLVM_READONLY
int getGlobalSaddrOp(uint16_t Opcode);
LLVM_READONLY
int getVCMPXNoSDstOp(uint16_t Opcode);
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);

13
lib/Target/AMDGPU/SIInstrInfo.td
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@ -892,7 +892,9 @@ def KImmFP16MatchClass : KImmMatchClass<16>;
def f16kimm : kimmOperand<i16>;
def VOPDstS64 : VOPDstOperand <SReg_64>;
def VOPDstS64 : VOPDstOperand <SReg_64> {
let PrintMethod = "printVOPDst";
}
class FPInputModsMatchClass <int opSize> : AsmOperandClass {
let Name = "RegOrImmWithFP"#opSize#"InputMods";
@ -2171,6 +2173,15 @@ def getGlobalSaddrOp : InstrMapping {
let ValueCols = [["1"]];
}
// Maps a v_cmpx opcode with sdst to opcode without sdst.
def getVCMPXNoSDstOp : InstrMapping {
let FilterClass = "VCMPXNoSDstTable";
let RowFields = ["NoSDstOp"];
let ColFields = ["HasSDst"];
let KeyCol = ["1"];
let ValueCols = [["0"]];
}
include "SIInstructions.td"
include "DSInstructions.td"

2
lib/Target/AMDGPU/VOP2Instructions.td
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@ -345,7 +345,7 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*
// Read in from vcc or arbitrary SGPR.
def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
let Asm32 = "$vdst, $src0, $src1, vcc";
let Asm32 = "$vdst, $src0, $src1";
let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2";
let AsmSDWA = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
let AsmSDWA9 = "$vdst, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";

898
lib/Target/AMDGPU/VOPCInstructions.td
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File diff suppressed because it is too large Load Diff

3
test/MC/AMDGPU/vop2-err.s
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@ -8,9 +8,6 @@
v_mul_i32_i24 v1, v2, 100
// CHECK: error: invalid operand for instruction
v_cndmask_b32 v1, v2, v3
// CHECK: error: too few operands for instruction
//===----------------------------------------------------------------------===//
// _e32 checks
//===----------------------------------------------------------------------===//