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[NFC][AMDGPU] Corrections to AMD GPU initial kernel launch documentation
Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D99223
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@ -4280,12 +4280,11 @@ SGPR register initial state is defined in
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(enable_sgpr_dispatch_id) dispatch packet being
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executed.
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then Flat Scratch Init 2 See
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:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
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(enable_sgpr_flat_scratch :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
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_init)
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then Private Segment Size 1 The 32-bit byte size of a
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(enable_sgpr_private single
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work-item's
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scratch_segment_size) memory
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allocation. This is the
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(enable_sgpr_private single work-item's memory
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_segment_size) allocation. This is the
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value from the kernel
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dispatch packet Private
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Segment Byte Size rounded up
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@ -4303,36 +4302,6 @@ SGPR register initial state is defined in
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may be needed for GFX9-GFX10 which
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changes the meaning of the
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Flat Scratch Init value.
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then Grid Work-Group Count X 1 32-bit count of the number of
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(enable_sgpr_grid work-groups in the X dimension
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_workgroup_count_X) for the grid being
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executed. Computed from the
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fields in the kernel dispatch
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packet as ((grid_size.x +
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workgroup_size.x - 1) /
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workgroup_size.x).
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then Grid Work-Group Count Y 1 32-bit count of the number of
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(enable_sgpr_grid work-groups in the Y dimension
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_workgroup_count_Y && for the grid being
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less than 16 previous executed. Computed from the
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SGPRs) fields in the kernel dispatch
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packet as ((grid_size.y +
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workgroup_size.y - 1) /
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workgroupSize.y).
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Only initialized if <16
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previous SGPRs initialized.
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then Grid Work-Group Count Z 1 32-bit count of the number of
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(enable_sgpr_grid work-groups in the Z dimension
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_workgroup_count_Z && for the grid being
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less than 16 previous executed. Computed from the
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SGPRs) fields in the kernel dispatch
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packet as ((grid_size.z +
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workgroup_size.z - 1) /
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workgroupSize.z).
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Only initialized if <16
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previous SGPRs initialized.
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then Work-Group Id X 1 32-bit work-group id in X
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(enable_sgpr_workgroup_id dimension of grid for
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_X) wavefront.
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