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Added an alternate form of register-register CMP
to the Intel instruction tables. llvm-svn: 82081
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@ -1081,6 +1081,8 @@ def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
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"cmp{q}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp GR64:$src1, GR64:$src2),
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(implicit EFLAGS)]>;
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def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
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"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
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def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
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"cmp{q}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp (loadi64 addr:$src1), GR64:$src2),
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@ -3189,6 +3189,12 @@ def CMP32rm : I<0x3B, MRMSrcMem,
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"cmp{l}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp GR32:$src1, (loadi32 addr:$src2)),
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(implicit EFLAGS)]>;
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def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
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"cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
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def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
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"cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
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def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
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"cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
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def CMP8ri : Ii8<0x80, MRM7r,
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(outs), (ins GR8:$src1, i8imm:$src2),
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"cmp{b}\t{$src2, $src1|$src1, $src2}",
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