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https://github.com/RPCS3/llvm-mirror.git
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Fix to 80-col.
llvm-svn: 107684
This commit is contained in:
parent
0e0d4bcfc8
commit
383df15267
@ -55,8 +55,8 @@ protected:
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const TargetInstrInfo *tii;
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const TargetInstrInfo *tii;
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const TargetRegisterInfo *tri;
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const TargetRegisterInfo *tri;
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VirtRegMap *vrm;
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VirtRegMap *vrm;
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/// Construct a spiller base.
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/// Construct a spiller base.
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SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
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SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
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: mf(mf), lis(lis), vrm(vrm)
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: mf(mf), lis(lis), vrm(vrm)
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{
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{
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@ -97,7 +97,7 @@ protected:
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do {
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do {
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++regItr;
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++regItr;
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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// Collect uses & defs for this instr.
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// Collect uses & defs for this instr.
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SmallVector<unsigned, 2> indices;
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SmallVector<unsigned, 2> indices;
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bool hasUse = false;
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bool hasUse = false;
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@ -117,7 +117,7 @@ protected:
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vrm->assignVirt2StackSlot(newVReg, ss);
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vrm->assignVirt2StackSlot(newVReg, ss);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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newLI->weight = HUGE_VALF;
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newLI->weight = HUGE_VALF;
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// Update the reg operands & kill flags.
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// Update the reg operands & kill flags.
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for (unsigned i = 0; i < indices.size(); ++i) {
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for (unsigned i = 0; i < indices.size(); ++i) {
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unsigned mopIdx = indices[i];
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unsigned mopIdx = indices[i];
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@ -217,7 +217,7 @@ namespace {
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/// When a call to spill is placed this spiller will first try to break the
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/// When a call to spill is placed this spiller will first try to break the
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/// interval up into its component values (one new interval per value).
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/// interval up into its component values (one new interval per value).
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/// If this fails, or if a call is placed to spill a previously split interval
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/// If this fails, or if a call is placed to spill a previously split interval
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/// then the spiller falls back on the standard spilling mechanism.
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/// then the spiller falls back on the standard spilling mechanism.
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class SplittingSpiller : public StandardSpiller {
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class SplittingSpiller : public StandardSpiller {
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public:
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public:
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SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
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SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
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@ -243,7 +243,7 @@ private:
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MachineRegisterInfo *mri;
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MachineRegisterInfo *mri;
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const TargetInstrInfo *tii;
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const TargetInstrInfo *tii;
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const TargetRegisterInfo *tri;
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const TargetRegisterInfo *tri;
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DenseSet<LiveInterval*> alreadySplit;
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DenseSet<LiveInterval*> alreadySplit;
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bool worthTryingToSplit(LiveInterval *li) const {
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bool worthTryingToSplit(LiveInterval *li) const {
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@ -260,18 +260,18 @@ private:
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SmallVector<VNInfo*, 4> vnis;
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SmallVector<VNInfo*, 4> vnis;
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std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
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std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
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for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
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for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
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vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
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vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
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VNInfo *vni = *vniItr;
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VNInfo *vni = *vniItr;
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// Skip unused VNIs.
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// Skip unused VNIs.
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if (vni->isUnused())
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if (vni->isUnused())
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continue;
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continue;
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DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
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DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
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LiveInterval *splitInterval = extractVNI(li, vni);
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LiveInterval *splitInterval = extractVNI(li, vni);
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if (splitInterval != 0) {
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if (splitInterval != 0) {
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DEBUG(dbgs() << *splitInterval << "\n");
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DEBUG(dbgs() << *splitInterval << "\n");
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added.push_back(splitInterval);
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added.push_back(splitInterval);
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@ -283,12 +283,12 @@ private:
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} else {
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} else {
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DEBUG(dbgs() << "0\n");
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DEBUG(dbgs() << "0\n");
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}
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}
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}
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}
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DEBUG(dbgs() << "Original LI: " << *li << "\n");
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DEBUG(dbgs() << "Original LI: " << *li << "\n");
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// If there original interval still contains some live ranges
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// If there original interval still contains some live ranges
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// add it to added and alreadySplit.
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// add it to added and alreadySplit.
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if (!li->empty()) {
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if (!li->empty()) {
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added.push_back(li);
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added.push_back(li);
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alreadySplit.insert(li);
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alreadySplit.insert(li);
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@ -312,7 +312,7 @@ private:
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
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VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
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VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
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// Start by copying all live ranges in the VN to the new interval.
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// Start by copying all live ranges in the VN to the new interval.
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for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
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for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
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rItr != rEnd; ++rItr) {
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rItr != rEnd; ++rItr) {
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if (rItr->valno == vni) {
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if (rItr->valno == vni) {
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@ -320,7 +320,7 @@ private:
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}
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}
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}
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}
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// Erase the old VNI & ranges.
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// Erase the old VNI & ranges.
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li->removeValNo(vni);
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li->removeValNo(vni);
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// Collect all current uses of the register belonging to the given VNI.
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// Collect all current uses of the register belonging to the given VNI.
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@ -367,8 +367,8 @@ private:
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newVNI->setIsPHIDef(false); // not a PHI def anymore.
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newVNI->setIsPHIDef(false); // not a PHI def anymore.
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newVNI->setIsDefAccurate(true);
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newVNI->setIsDefAccurate(true);
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} else {
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} else {
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// non-PHI def. Rename the def. If it's two-addr that means renaming the use
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// non-PHI def. Rename the def. If it's two-addr that means renaming the
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// and inserting a new copy too.
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// use and inserting a new copy too.
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MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
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MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
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// We'll rename this now, so we can remove it from uses.
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// We'll rename this now, so we can remove it from uses.
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uses.erase(defInst);
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uses.erase(defInst);
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@ -384,7 +384,7 @@ private:
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twoAddrUseIsUndef = true;
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twoAddrUseIsUndef = true;
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}
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}
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}
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}
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SlotIndex defIdx = lis->getInstructionIndex(defInst);
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SlotIndex defIdx = lis->getInstructionIndex(defInst);
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newVNI->def = defIdx.getDefIndex();
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newVNI->def = defIdx.getDefIndex();
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@ -402,9 +402,9 @@ private:
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true, lis->getVNInfoAllocator());
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true, lis->getVNInfoAllocator());
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LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
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LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
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newLI->addRange(copyRange);
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newLI->addRange(copyRange);
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}
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}
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}
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}
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for (std::set<MachineInstr*>::iterator
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for (std::set<MachineInstr*>::iterator
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usesItr = uses.begin(), usesEnd = uses.end();
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usesItr = uses.begin(), usesEnd = uses.end();
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usesItr != usesEnd; ++usesItr) {
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usesItr != usesEnd; ++usesItr) {
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@ -424,7 +424,7 @@ private:
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// Check if this instr is two address.
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// Check if this instr is two address.
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unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
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unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
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bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
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bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
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// Rename uses (and defs for two-address instrs).
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// Rename uses (and defs for two-address instrs).
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for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
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for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
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MachineOperand &mo = useInst->getOperand(i);
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MachineOperand &mo = useInst->getOperand(i);
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@ -440,8 +440,8 @@ private:
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// reg.
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// reg.
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MachineBasicBlock *useMBB = useInst->getParent();
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MachineBasicBlock *useMBB = useInst->getParent();
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MachineBasicBlock::iterator useItr(useInst);
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MachineBasicBlock::iterator useItr(useInst);
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tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc, trc,
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tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc,
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DebugLoc());
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trc, DebugLoc());
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MachineInstr *copyMI = llvm::next(useItr);
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MachineInstr *copyMI = llvm::next(useItr);
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copyMI->addRegisterKilled(newVReg, tri);
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copyMI->addRegisterKilled(newVReg, tri);
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SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
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SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
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