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Allow widening of extract subvector
llvm-svn: 84279
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4790ea6ca2
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@ -617,6 +617,7 @@ private:
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SDValue WidenVecOp_BIT_CONVERT(SDNode *N);
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SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
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SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
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SDValue WidenVecOp_STORE(SDNode* N);
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SDValue WidenVecOp_Convert(SDNode *N);
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@ -1789,6 +1789,7 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
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case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
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case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
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case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
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case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
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case ISD::STORE: Res = WidenVecOp_STORE(N); break;
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@ -1893,6 +1894,12 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
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return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
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}
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SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
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SDValue InOp = GetWidenedVector(N->getOperand(0));
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
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N->getValueType(0), InOp, N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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SDValue InOp = GetWidenedVector(N->getOperand(0));
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
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