RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Place new constant node in topological order in X86DAGToDAGISel::matchBitExtract.

Browse Source 
Fixes PR47525
This commit is contained in:
Craig Topper 2020-09-14 16:28:11 -07:00
parent 371fcdc0f3
commit 3883d98619
2 changed files with 43 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -3502,6 +3502,7 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
// Shift NBits left by 8 bits, thus producing 'control'.
// This makes the low 8 bits to be zero.
SDValue C8 = CurDAG->getConstant(8, DL, MVT::i8);
insertDAGNode(*CurDAG, SDValue(Node, 0), C8);
SDValue Control = CurDAG->getNode(ISD::SHL, DL, MVT::i32, NBits, C8);
insertDAGNode(*CurDAG, SDValue(Node, 0), Control);

42
test/CodeGen/X86/pr47525.ll Normal file
View File

@ -0,0 +1,42 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=bmi | FileCheck %s
@a = external local_unnamed_addr global i32, align 4
@f = external local_unnamed_addr global i32, align 4
define void @g(i32* %x, i32* %y, i32* %z) {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: sete %cl
; CHECK-NEXT: addl %ecx, %ecx
; CHECK-NEXT: orl (%rdi), %ecx
; CHECK-NEXT: movl $0, (%rsi)
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: shll $8, %eax
; CHECK-NEXT: bextrl %eax, {{.*}}(%rip), %eax
; CHECK-NEXT: orl %ecx, %eax
; CHECK-NEXT: movl %eax, (%rdx)
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @a, align 4
%1 = tail call i32 asm "", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0)
%2 = icmp eq i32 %1, 0
%shl1 = select i1 %2, i32 2, i32 0
%3 = load i32, i32* %x, align 4
%or = or i32 %3, %shl1
store i32 0, i32* %y, align 4
%4 = tail call i32 asm "", "=r,~{dirflag},~{fpsr},~{flags}"()
%notmask = shl nsw i32 -1, %4
%sub = xor i32 %notmask, -1
%5 = load i32, i32* @f, align 4
%and4 = and i32 %5, %sub
%or6 = or i32 %and4, %or
store i32 %or6, i32* %z, align 4
ret void
}