Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.

llvm-svn: 48995

include/llvm/Target/TargetInstrInfo.h

@@ -112,6 +112,13 @@ public:
     return 0;
   }
 
+  /// reMaterialize - Re-issue the specified 'original' instruction at the
+  /// specific location targeting a new destination register.
+  virtual void reMaterialize(MachineBasicBlock &MBB,
+                             MachineBasicBlock::iterator MI,
+                             unsigned DestReg,
+                             const MachineInstr *Orig) const = 0;
+
   /// isInvariantLoad - Return true if the specified instruction (which is
   /// marked mayLoad) is loading from a location whose value is invariant across
   /// the function.  For example, loading a value from the constant pool or from
@@ -397,7 +404,10 @@ public:
                                          unsigned &OpIdx) const;
   virtual bool PredicateInstruction(MachineInstr *MI,
                               const std::vector<MachineOperand> &Pred) const;
-  
+  virtual void reMaterialize(MachineBasicBlock &MBB,
+                             MachineBasicBlock::iterator MI,
+                             unsigned DestReg,
+                             const MachineInstr *Orig) const;
 };
 
 } // End llvm namespace

include/llvm/Target/TargetRegisterInfo.h

@@ -487,13 +487,6 @@ public:
     return NULL;
   }
 
-  /// reMaterialize - Re-issue the specified 'original' instruction at the
-  /// specific location targeting a new destination register.
-  virtual void reMaterialize(MachineBasicBlock &MBB,
-                             MachineBasicBlock::iterator MI,
-                             unsigned DestReg,
-                             const MachineInstr *Orig) const = 0;
-
   /// targetHandlesStackFrameRounding - Returns true if the target is
   /// responsible for rounding up the stack frame (probably at emitPrologue
   /// time).

lib/CodeGen/TargetInstrInfoImpl.cpp

@@ -84,3 +84,13 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
   }
   return MadeChange;
 }
+
+void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator I,
+                                        unsigned DestReg,
+                                        const MachineInstr *Orig) const {
+  MachineInstr *MI = Orig->clone();
+  MI->getOperand(0).setReg(DestReg);
+  MBB.insert(I, MI);
+}
+

lib/CodeGen/VirtRegMap.cpp

@@ -642,9 +642,10 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
 static void ReMaterialize(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator &MII,
                           unsigned DestReg, unsigned Reg,
+                          const TargetInstrInfo *TII,
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
-  TRI->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
+  TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
   MachineInstr *NewMI = prior(MII);
   for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = NewMI->getOperand(i);
@@ -784,7 +785,7 @@ namespace {
             
             MachineBasicBlock::iterator MII = MI;
             if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
-              ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TRI, VRM);
+              ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM);
             } else {
               TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
                                         NewOp.StackSlotOrReMat, AliasRC);
@@ -1098,7 +1099,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
         unsigned Phys = VRM.getPhys(VirtReg);
         RegInfo->setPhysRegUsed(Phys);
         if (VRM.isReMaterialized(VirtReg)) {
-          ReMaterialize(MBB, MII, Phys, VirtReg, TRI, VRM);
+          ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM);
         } else {
           const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
           int SS = VRM.getStackSlot(VirtReg);
@@ -1351,7 +1352,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
       RegInfo->setPhysRegUsed(PhysReg);
       ReusedOperands.markClobbered(PhysReg);
       if (DoReMat) {
-        ReMaterialize(MBB, MII, PhysReg, VirtReg, TRI, VRM);
+        ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM);
       } else {
         const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
         TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);

lib/Target/ARM/ARMInstrInfo.cpp

@@ -141,6 +141,22 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
   return 0;
 }
 
+void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
+                                 MachineBasicBlock::iterator I,
+                                 unsigned DestReg,
+                                 const MachineInstr *Orig) const {
+  if (Orig->getOpcode() == ARM::MOVi2pieces) {
+    RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
+                         Orig->getOperand(2).getImm(),
+                         Orig->getOperand(3).getReg(), this, false);
+    return;
+  }
+
+  MachineInstr *MI = Orig->clone();
+  MI->getOperand(0).setReg(DestReg);
+  MBB.insert(I, MI);
+}
+
 static unsigned getUnindexedOpcode(unsigned Opc) {
   switch (Opc) {
   default: break;
@@ -934,3 +950,4 @@ unsigned ARM::GetFunctionSize(MachineFunction &MF) {
   }
   return FnSize;
 }
+

lib/Target/ARM/ARMInstrInfo.h

@@ -148,6 +148,9 @@ public:
   virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
   virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
   
+  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+                     unsigned DestReg, const MachineInstr *Orig) const;
+
   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
                                               MachineBasicBlock::iterator &MBBI,
                                               LiveVariables &LV) const;

lib/Target/ARM/ARMRegisterInfo.cpp

@@ -100,38 +100,21 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
 
 /// emitLoadConstPool - Emits a load from constpool to materialize the
 /// specified immediate.
-static void emitLoadConstPool(MachineBasicBlock &MBB,
+void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator &MBBI,
+                                        MachineBasicBlock::iterator &MBBI,
-                              unsigned DestReg, int Val,
+                                        unsigned DestReg, int Val,
-                              ARMCC::CondCodes Pred, unsigned PredReg,
+                                        unsigned Pred, unsigned PredReg,
-                              const TargetInstrInfo &TII, bool isThumb) {
+                                        const TargetInstrInfo *TII,
+                                        bool isThumb) const {
   MachineFunction &MF = *MBB.getParent();
   MachineConstantPool *ConstantPool = MF.getConstantPool();
   Constant *C = ConstantInt::get(Type::Int32Ty, Val);
   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
   if (isThumb)
-    BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
+    BuildMI(MBB, MBBI, TII->get(ARM::tLDRcp),DestReg).addConstantPoolIndex(Idx);
   else
-    BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
+    BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
-      .addReg(0).addImm(0).addImm((unsigned)Pred).addReg(PredReg);
+      .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
-}
-
-void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I,
-                                    unsigned DestReg,
-                                    const MachineInstr *Orig) const {
-  if (Orig->getOpcode() == ARM::MOVi2pieces) {
-    emitLoadConstPool(MBB, I, DestReg,
-                      Orig->getOperand(1).getImm(),
-                      (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
-                      Orig->getOperand(3).getReg(),
-                      TII, false);
-    return;
-  }
-
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
 }
 
 /// isLowRegister - Returns true if the register is low register r0-r7.
@@ -344,7 +327,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
       BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
         .addReg(LdReg, false, false, true);
     } else
-      emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0, TII, true);
+      MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, ARMCC::AL, 0,&TII,true);
 
     // Emit add / sub.
     int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@@ -785,7 +768,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
           emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
                                    Offset, false, TII, *this);
         else {
-          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
+          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
           UseRR = true;
         }
       } else
@@ -822,7 +805,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
           emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
                                    Offset, false, TII, *this);
         else {
-          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, TII, true);
+          emitLoadConstPool(MBB, II, TmpReg, Offset, ARMCC::AL, 0, &TII, true);
           UseRR = true;
         }
       } else
@@ -1402,4 +1385,3 @@ int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 }
 
 #include "ARMGenRegisterInfo.inc"
-

lib/Target/ARM/ARMRegisterInfo.h

@@ -32,14 +32,19 @@ private:
 public:
   ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
 
+  /// emitLoadConstPool - Emits a load from constpool to materialize the
+  /// specified immediate.
+  void emitLoadConstPool(MachineBasicBlock &MBB,
+                         MachineBasicBlock::iterator &MBBI,
+                         unsigned DestReg, int Val,
+                         unsigned Pred, unsigned PredReg,
+                         const TargetInstrInfo *TII, bool isThumb) const;
+
   /// getRegisterNumbering - Given the enum value for some register, e.g.
   /// ARM::LR, return the number that it corresponds to (e.g. 14).
   static unsigned getRegisterNumbering(unsigned RegEnum);
 
   /// Code Generation virtual methods...
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 
   const TargetRegisterClass* const*

lib/Target/Alpha/AlphaRegisterInfo.cpp

@@ -58,15 +58,6 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
 {
 }
 
-void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                      MachineBasicBlock::iterator I,
-                                      unsigned DestReg,
-                                      const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
                                                                          const {
   static const unsigned CalleeSavedRegs[] = {

lib/Target/Alpha/AlphaRegisterInfo.h

@@ -28,9 +28,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
   AlphaRegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses(

lib/Target/CellSPU/SPURegisterInfo.cpp

@@ -191,15 +191,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
 {
 }
 
-void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I,
-                                    unsigned DestReg,
-                                    const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 // SPU's 128-bit registers used for argument passing:
 static const unsigned SPU_ArgRegs[] = {
   SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,

lib/Target/CellSPU/SPURegisterInfo.h

@@ -41,9 +41,6 @@ namespace llvm {
      */
     static unsigned getRegisterNumbering(unsigned RegEnum);
 
-    void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                       unsigned DestReg, const MachineInstr *Orig) const;
-    
     //! Return the array of callee-saved registers
     virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
 

lib/Target/IA64/IA64RegisterInfo.cpp

@@ -37,15 +37,6 @@ IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
   : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
     TII(tii) {}
 
-void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I,
-                                     unsigned DestReg,
-                                     const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
                                                                          const {
   static const unsigned CalleeSavedRegs[] = {

lib/Target/IA64/IA64RegisterInfo.h

@@ -27,9 +27,6 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
   IA64RegisterInfo(const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses(

lib/Target/Mips/MipsRegisterInfo.cpp

@@ -84,16 +84,6 @@ getRegisterNumbering(unsigned RegEnum)
   return 0; // Not reached
 }
 
-void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 
-                                      MachineBasicBlock::iterator I,
-                                      unsigned DestReg, 
-                                      const MachineInstr *Orig) const 
-{
-    MachineInstr *MI = Orig->clone();
-    MI->getOperand(0).setReg(DestReg);
-    MBB.insert(I, MI);
-}
-
 //===----------------------------------------------------------------------===//
 //
 // Callee Saved Registers methods 

lib/Target/Mips/MipsRegisterInfo.h

@@ -32,9 +32,6 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
   static unsigned getRegisterNumbering(unsigned RegEnum);
 
   /// Code Generation virtual methods...
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 
   const TargetRegisterClass* const*

lib/Target/PowerPC/PPCRegisterInfo.cpp

@@ -136,15 +136,6 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
 }
 
-void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I,
-                                    unsigned DestReg,
-                                    const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 const unsigned*
 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   // 32-bit Darwin calling convention. 

lib/Target/PowerPC/PPCRegisterInfo.h

@@ -36,9 +36,6 @@ public:
   static unsigned getRegisterNumbering(unsigned RegEnum);
 
   /// Code Generation virtual methods...
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 
   const TargetRegisterClass* const*

lib/Target/Sparc/SparcRegisterInfo.cpp

@@ -30,15 +30,6 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
     Subtarget(st), TII(tii) {
 }
 
-void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                      MachineBasicBlock::iterator I,
-                                      unsigned DestReg,
-                                      const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
                                                                          const {
   static const unsigned CalleeSavedRegs[] = { 0 };

lib/Target/Sparc/SparcRegisterInfo.h

@@ -30,9 +30,6 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
   SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...  
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
 
   const TargetRegisterClass* const* getCalleeSavedRegClasses(

lib/Target/X86/X86InstrInfo.cpp

@@ -820,6 +820,34 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
   return true;
 }
 
+void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
+                                 MachineBasicBlock::iterator I,
+                                 unsigned DestReg,
+                                 const MachineInstr *Orig) const {
+  // MOV32r0 etc. are implemented with xor which clobbers condition code.
+  // Re-materialize them as movri instructions to avoid side effects.
+  switch (Orig->getOpcode()) {
+  case X86::MOV8r0:
+    BuildMI(MBB, I, get(X86::MOV8ri), DestReg).addImm(0);
+    break;
+  case X86::MOV16r0:
+    BuildMI(MBB, I, get(X86::MOV16ri), DestReg).addImm(0);
+    break;
+  case X86::MOV32r0:
+    BuildMI(MBB, I, get(X86::MOV32ri), DestReg).addImm(0);
+    break;
+  case X86::MOV64r0:
+    BuildMI(MBB, I, get(X86::MOV64ri32), DestReg).addImm(0);
+    break;
+  default: {
+    MachineInstr *MI = Orig->clone();
+    MI->getOperand(0).setReg(DestReg);
+    MBB.insert(I, MI);
+    break;
+  }
+  }
+}
+
 /// isInvariantLoad - Return true if the specified instruction (which is marked
 /// mayLoad) is loading from a location whose value is invariant across the
 /// function.  For example, loading a value from the constant pool or from

lib/Target/X86/X86InstrInfo.h

@@ -258,7 +258,11 @@ public:
                    unsigned& destReg) const;
   unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
   unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+
   bool isReallyTriviallyReMaterializable(MachineInstr *MI) const;
+  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+                     unsigned DestReg, const MachineInstr *Orig) const;
+
   bool isInvariantLoad(MachineInstr *MI) const;
 
   /// convertToThreeAddress - This method must be implemented by targets that

lib/Target/X86/X86RegisterInfo.cpp

@@ -155,34 +155,6 @@ X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   return NULL;
 }
 
-void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I,
-                                    unsigned DestReg,
-                                    const MachineInstr *Orig) const {
-  // MOV32r0 etc. are implemented with xor which clobbers condition code.
-  // Re-materialize them as movri instructions to avoid side effects.
-  switch (Orig->getOpcode()) {
-  case X86::MOV8r0:
-    BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0);
-    break;
-  case X86::MOV16r0:
-    BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0);
-    break;
-  case X86::MOV32r0:
-    BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0);
-    break;
-  case X86::MOV64r0:
-    BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0);
-    break;
-  default: {
-    MachineInstr *MI = Orig->clone();
-    MI->getOperand(0).setReg(DestReg);
-    MBB.insert(I, MI);
-    break;
-  }
-  }
-}
-
 const unsigned *
 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   static const unsigned CalleeSavedRegs32Bit[] = {

lib/Target/X86/X86RegisterInfo.h

@@ -97,9 +97,6 @@ public:
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const;
 
-  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                     unsigned DestReg, const MachineInstr *Orig) const;
-
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.
   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;