diff --git a/lib/CodeGen/Analysis.cpp b/lib/CodeGen/Analysis.cpp index ebeff1fec30..5d1b00463dc 100644 --- a/lib/CodeGen/Analysis.cpp +++ b/lib/CodeGen/Analysis.cpp @@ -43,13 +43,11 @@ unsigned llvm::ComputeLinearIndex(Type *Ty, // Given a struct type, recursively traverse the elements. if (StructType *STy = dyn_cast(Ty)) { - for (StructType::element_iterator EB = STy->element_begin(), - EI = EB, - EE = STy->element_end(); - EI != EE; ++EI) { - if (Indices && *Indices == unsigned(EI - EB)) - return ComputeLinearIndex(*EI, Indices+1, IndicesEnd, CurIndex); - CurIndex = ComputeLinearIndex(*EI, nullptr, nullptr, CurIndex); + for (auto I : llvm::enumerate(STy->elements())) { + Type *ET = I.value(); + if (Indices && *Indices == I.index()) + return ComputeLinearIndex(ET, Indices + 1, IndicesEnd, CurIndex); + CurIndex = ComputeLinearIndex(ET, nullptr, nullptr, CurIndex); } assert(!Indices && "Unexpected out of bound"); return CurIndex; diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index e1fa78d13f0..1eed0ec5bbb 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -1360,12 +1360,9 @@ unsigned ConnectedVNInfoEqClasses::Classify(const LiveRange &LR) { void ConnectedVNInfoEqClasses::Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI) { // Rewrite instructions. - for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg()), - RE = MRI.reg_end(); - RI != RE;) { - MachineOperand &MO = *RI; - MachineInstr *MI = RI->getParent(); - ++RI; + for (MachineOperand &MO : + llvm::make_early_inc_range(MRI.reg_operands(LI.reg()))) { + MachineInstr *MI = MO.getParent(); const VNInfo *VNI; if (MI->isDebugValue()) { // DBG_VALUE instructions don't have slot indexes, so get the index of diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 387b5e6519e..b9c5ca22fc3 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1459,9 +1459,8 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { if (isa(C) || isa(C)) { SmallVector Constants; - for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); - OI != OE; ++OI) { - SDNode *Val = getValue(*OI).getNode(); + for (const Use &U : C->operands()) { + SDNode *Val = getValue(U).getNode(); // If the operand is an empty aggregate, there are no values. if (!Val) continue; // Add each leaf value from the operand to the Constants list diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 500bdb401b9..c6c924f1ea6 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2266,10 +2266,8 @@ bool TargetLowering::SimplifyDemandedBits( if (DemandedBits.isSubsetOf(Known.Zero | Known.One)) { // Avoid folding to a constant if any OpaqueConstant is involved. const SDNode *N = Op.getNode(); - for (SDNodeIterator I = SDNodeIterator::begin(N), - E = SDNodeIterator::end(N); - I != E; ++I) { - SDNode *Op = *I; + for (SDNode *Op : + llvm::make_range(SDNodeIterator::begin(N), SDNodeIterator::end(N))) { if (ConstantSDNode *C = dyn_cast(Op)) if (C->isOpaque()) return false; @@ -4564,11 +4562,10 @@ TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, if (!isLegalRC(*RI, *RC)) continue; - for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); - I != E; ++I) { - if (RegName.equals_lower(RI->getRegAsmName(*I))) { + for (const MCPhysReg &PR : *RC) { + if (RegName.equals_lower(RI->getRegAsmName(PR))) { std::pair S = - std::make_pair(*I, RC); + std::make_pair(PR, RC); // If this register class has the requested value type, return it, // otherwise keep searching and return the first class found diff --git a/lib/CodeGen/SplitKit.cpp b/lib/CodeGen/SplitKit.cpp index 22cd63e3215..d778a9e8c3e 100644 --- a/lib/CodeGen/SplitKit.cpp +++ b/lib/CodeGen/SplitKit.cpp @@ -1270,11 +1270,9 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { SmallVector ExtPoints; - for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()), - RE = MRI.reg_end(); RI != RE;) { - MachineOperand &MO = *RI; + for (MachineOperand &MO : + llvm::make_early_inc_range(MRI.reg_operands(Edit->getReg()))) { MachineInstr *MI = MO.getParent(); - ++RI; // LiveDebugVariables should have handled all DBG_VALUE instructions. if (MI->isDebugValue()) { LLVM_DEBUG(dbgs() << "Zapping " << *MI); diff --git a/lib/CodeGen/WinEHPrepare.cpp b/lib/CodeGen/WinEHPrepare.cpp index 36919ca0bfc..0e5d5e4d936 100644 --- a/lib/CodeGen/WinEHPrepare.cpp +++ b/lib/CodeGen/WinEHPrepare.cpp @@ -1023,11 +1023,10 @@ void WinEHPrepare::removeImplausibleInstructions(Function &F) { void WinEHPrepare::cleanupPreparedFunclets(Function &F) { // Clean-up some of the mess we made by removing useles PHI nodes, trivial // branches, etc. - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE;) { - BasicBlock *BB = &*FI++; - SimplifyInstructionsInBlock(BB); - ConstantFoldTerminator(BB, /*DeleteDeadConditions=*/true); - MergeBlockIntoPredecessor(BB); + for (BasicBlock &BB : llvm::make_early_inc_range(F)) { + SimplifyInstructionsInBlock(&BB); + ConstantFoldTerminator(&BB, /*DeleteDeadConditions=*/true); + MergeBlockIntoPredecessor(&BB); } // We might have some unreachable blocks after cleaning up some impossible @@ -1107,9 +1106,7 @@ AllocaInst *WinEHPrepare::insertPHILoads(PHINode *PN, Function &F) { // Otherwise, we have a PHI on a terminator EHPad, and we give up and insert // loads of the slot before every use. DenseMap Loads; - for (Value::use_iterator UI = PN->use_begin(), UE = PN->use_end(); - UI != UE;) { - Use &U = *UI++; + for (Use &U : llvm::make_early_inc_range(PN->uses())) { auto *UsingInst = cast(U.getUser()); if (isa(UsingInst) && UsingInst->getParent()->isEHPad()) { // Use is on an EH pad phi. Leave it alone; we'll insert loads and