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revert r338206 because the test does not pass
Example of bot failure: http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5107/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Ainline-asm-operand-implicit-cast.ll llvm-svn: 338214
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Sanjay Patel
parent
64ee418412
commit
38f01067ac
@ -7198,11 +7198,10 @@ static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
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/// uses features that we can't model on machineinstrs, we have SDISel do the
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/// allocation. This produces generally horrible, but correct, code.
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///
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/// OpInfo describes the operand
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/// RefOpInfo describes the matching operand if any, the operand otherwise
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/// OpInfo describes the operand.
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static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
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const SDLoc &DL, SDISelAsmOperandInfo &OpInfo,
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SDISelAsmOperandInfo &RefOpInfo) {
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const SDLoc &DL,
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SDISelAsmOperandInfo &OpInfo) {
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LLVMContext &Context = *DAG.getContext();
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MachineFunction &MF = DAG.getMachineFunction();
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@ -7212,8 +7211,8 @@ static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
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// If this is a constraint for a single physreg, or a constraint for a
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// register class, find it.
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std::pair<unsigned, const TargetRegisterClass *> PhysReg =
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TLI.getRegForInlineAsmConstraint(&TRI, RefOpInfo.ConstraintCode,
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RefOpInfo.ConstraintVT);
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TLI.getRegForInlineAsmConstraint(&TRI, OpInfo.ConstraintCode,
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OpInfo.ConstraintVT);
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unsigned NumRegs = 1;
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if (OpInfo.ConstraintVT != MVT::Other) {
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@ -7255,11 +7254,6 @@ static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
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NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
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}
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// No need to allocate a matching input constraint since the constraint it's
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// matching to has already been allocated.
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if (OpInfo.isMatchingInputConstraint())
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return;
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MVT RegVT;
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EVT ValueVT = OpInfo.ConstraintVT;
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@ -7508,27 +7502,19 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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// If this constraint is for a specific register, allocate it before
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// anything else.
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SDISelAsmOperandInfo &RefOpInfo =
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OpInfo.isMatchingInputConstraint()
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? ConstraintOperands[OpInfo.getMatchedOperand()]
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: ConstraintOperands[i];
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if (RefOpInfo.ConstraintType == TargetLowering::C_Register)
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GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
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if (OpInfo.ConstraintType == TargetLowering::C_Register)
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GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
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}
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// Third pass - Loop over all of the operands, assigning virtual or physregs
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// to register class operands.
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for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
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SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
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SDISelAsmOperandInfo &RefOpInfo =
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OpInfo.isMatchingInputConstraint()
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? ConstraintOperands[OpInfo.getMatchedOperand()]
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: ConstraintOperands[i];
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// C_Register operands have already been allocated, Other/Memory don't need
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// to be.
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if (RefOpInfo.ConstraintType == TargetLowering::C_RegisterClass)
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GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo, RefOpInfo);
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if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
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GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
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}
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// AsmNodeOperands - The operands for the ISD::INLINEASM node.
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@ -17,42 +17,6 @@ define arm_aapcscc double @zerobits_double_soft() #0 {
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; soft float ABI
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define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_in_op_soft
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; CHECK: mov r0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_soft
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; CHECK: mov r1, r0
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float input
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; with soft float ABI
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define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" }
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@ -75,48 +39,4 @@ define double @zerobits_double_hard() #1 {
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; hard float ABI
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define float @flt_gpr_matching_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK: mov r0, r0
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; CHECK: vmov s0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; hard float ABI
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define double @dbl_gpr_matching_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_hard
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; CHECK: vmov r0, r1, d0
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; CHECK: mov r1, r0
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; CHECK: vmov d0, r0, r1
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float
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; input with hard float ABI
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define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r3, s0
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; CHECK: mov r3, r3
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; CHECK: vmov s0, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with hard float ABI
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define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r2, r3, d0
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; CHECK: mov r3, r2
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; CHECK: vmov d0, r2, r3
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" }
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