RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
Code Issues Projects Releases Wiki Activity

[ARM GlobalISel] Add inst selector tests for G_SITOFP and G_UITOFP

Browse Source 
These are handled by the TableGen'erated code.

llvm-svn: 323732
This commit is contained in:
Diana Picus 2018-01-30 09:15:27 +00:00
parent 292ff8bb7e
commit 390217c22f
1 changed files with 113 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -38,6 +38,11 @@
define void @test_fptoui_s32() #0 { ret void }
define void @test_fptoui_s64() #0 { ret void }
define void @test_sitofp_s32() #0 { ret void }
define void @test_sitofp_s64() #0 { ret void }
define void @test_uitofp_s32() #0 { ret void }
define void @test_uitofp_s64() #0 { ret void }
define void @test_sub_s32() { ret void }
define void @test_sub_imm_s32() { ret void }
define void @test_sub_rev_imm_s32() { ret void }
@ -898,6 +903,114 @@ body: |
; CHECK: BX_RET 14, %noreg, implicit %r0
...
---
name: test_sitofp_s32
# CHECK-LABEL: name: test_sitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, %noreg
%s0 = COPY %1(s32)
; CHECK: %s0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, %noreg, implicit %s0
...
---
name: test_sitofp_s64
# CHECK-LABEL: name: test_sitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, %noreg
%d0 = COPY %1(s64)
; CHECK: %d0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, %noreg, implicit %d0
...
---
name: test_uitofp_s32
# CHECK-LABEL: name: test_uitofp_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, %noreg
%s0 = COPY %1(s32)
; CHECK: %s0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, %noreg, implicit %s0
...
---
name: test_uitofp_s64
# CHECK-LABEL: name: test_uitofp_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: %r0
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, %noreg
%d0 = COPY %1(s64)
; CHECK: %d0 = COPY [[VREGR]]
BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, %noreg, implicit %d0
...
---
name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32
legalized: true