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[SelectionDAG] Add knowbits support for CONCAT_VECTOR opcode
llvm-svn: 287387
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422b019be0
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@ -2113,6 +2113,24 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
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}
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break;
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}
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case ISD::CONCAT_VECTORS: {
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// Split DemandedElts and test each of the demanded subvectors.
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KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
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EVT SubVectorVT = Op.getOperand(0).getValueType();
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unsigned NumSubVectorElts = SubVectorVT.getVectorNumElements();
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unsigned NumSubVectors = Op.getNumOperands();
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for (unsigned i = 0; i != NumSubVectors; ++i) {
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APInt DemandedSub = DemandedElts.lshr(i * NumSubVectorElts);
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DemandedSub = DemandedSub.trunc(NumSubVectorElts);
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if (!!DemandedSub) {
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SDValue Sub = Op.getOperand(i);
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computeKnownBits(Sub, KnownZero2, KnownOne2, DemandedSub, Depth + 1);
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KnownOne &= KnownOne2;
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KnownZero &= KnownZero2;
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}
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}
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break;
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}
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case ISD::EXTRACT_SUBVECTOR: {
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// If we know the element index, just demand that subvector elements,
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// otherwise demand them all.
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@ -331,15 +331,8 @@ define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) n
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; X32-NEXT: vpand {{\.LCPI.*}}, %xmm1, %xmm1
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; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
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; X32-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,3,1,3]
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; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; X32-NEXT: vandps {{\.LCPI.*}}, %ymm2, %ymm2
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; X32-NEXT: vcvtdq2ps %ymm2, %ymm2
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; X32-NEXT: vpsrld $16, %xmm0, %xmm0
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; X32-NEXT: vpsrld $16, %xmm1, %xmm1
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; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; X32-NEXT: vcvtdq2ps %ymm0, %ymm0
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; X32-NEXT: vmulps {{\.LCPI.*}}, %ymm0, %ymm0
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; X32-NEXT: vaddps %ymm2, %ymm0, %ymm0
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; X32-NEXT: retl
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;
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; X64-LABEL: knownbits_mask_concat_uitofp:
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@ -348,15 +341,8 @@ define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) n
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; X64-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
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; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,3,1,3]
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; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
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; X64-NEXT: vandps {{.*}}(%rip), %ymm2, %ymm2
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; X64-NEXT: vcvtdq2ps %ymm2, %ymm2
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; X64-NEXT: vpsrld $16, %xmm0, %xmm0
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; X64-NEXT: vpsrld $16, %xmm1, %xmm1
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; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
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; X64-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0
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; X64-NEXT: vaddps %ymm2, %ymm0, %ymm0
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; X64-NEXT: retq
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%1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 131071, i32 -1>
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%2 = and <4 x i32> %a1, <i32 -1, i32 131071, i32 -1, i32 131071>
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