RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

Fix SPU to cope with vector insertelement to an undef position.

Browse Source 
We default to inserting to lane 0.

llvm-svn: 105722
This commit is contained in:
Kalle Raiskila 2010-06-09 09:58:17 +00:00
parent b547a95a7b
commit 392de86bb5
2 changed files with 21 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -2056,14 +2056,19 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
// use 0 when the lane to insert to is 'undef'
int64_t Idx=0;
if (IdxOp.getOpcode() != ISD::UNDEF) {
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
Idx = (CN->getSExtValue());
}
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
DAG.getConstant(CN->getSExtValue(), PtrVT));
DAG.getConstant(Idx, PtrVT));
SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
SDValue result =

15
test/CodeGen/CellSPU/vecinsert.ll
View File

@ -1,17 +1,19 @@
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep cbd %t1.s | count 5
; RUN: grep chd %t1.s | count 5
; RUN: grep cwd %t1.s | count 10
; RUN: grep cwd %t1.s | count 11
; RUN: grep -w il %t1.s | count 5
; RUN: grep -w ilh %t1.s | count 6
; RUN: grep iohl %t1.s | count 1
; RUN: grep ilhu %t1.s | count 4
; RUN: grep shufb %t1.s | count 26
; RUN: grep shufb %t1.s | count 27
; RUN: grep 17219 %t1.s | count 1
; RUN: grep 22598 %t1.s | count 1
; RUN: grep -- -39 %t1.s | count 1
; RUN: grep 24 %t1.s | count 1
; RUN: grep 1159 %t1.s | count 1
; RUN: FileCheck %s < %t1.s
; ModuleID = 'vecinsert.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
target triple = "spu-unknown-elf"
@ -118,3 +120,12 @@ entry:
store <2 x double> %tmp3, <2 x double>* %arrayidx
ret void
}
define <4 x i32> @undef_v4i32( i32 %param ) {
;CHECK: cwd
;CHECK: lqa
;CHECK: shufb
%val = insertelement <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i32 %param, i32 undef
ret <4 x i32> %val
}