RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Code Issues Projects Releases Wiki Activity

LowerTypeTests: Represent the memory region size with the constant size-1.

Browse Source 
This means that we can use a shorter instruction sequence in the case where
the size is a power of two and on the boundary between two representations.

Differential Revision: https://reviews.llvm.org/D28421

llvm-svn: 291706
This commit is contained in:
Peter Collingbourne 2017-01-11 21:32:10 +00:00
parent 9f4509ce02
commit 396740fa88
7 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/IR/ModuleSummaryIndex.h
View File

@ -317,10 +317,10 @@ struct TypeTestResolution {
/// All-Ones Bit Vectors")
} TheKind = Unsat;
/// Range of the size expressed as a bit width. For example, if the size is in
/// range [0,256), this number will be 8. This helps generate the most compact
/// Range of size-1 expressed as a bit width. For example, if the size is in
/// range [1,256], this number will be 8. This helps generate the most compact
/// instruction sequences.
unsigned SizeBitWidth = 0;
unsigned SizeM1BitWidth = 0;
};
struct TypeIdSummary {

2
include/llvm/IR/ModuleSummaryIndexYAML.h
View File

@ -29,7 +29,7 @@ template <> struct ScalarEnumerationTraits<TypeTestResolution::Kind> {
template <> struct MappingTraits<TypeTestResolution> {
static void mapping(IO &io, TypeTestResolution &res) {
io.mapOptional("Kind", res.TheKind);
io.mapOptional("SizeBitWidth", res.SizeBitWidth);
io.mapOptional("SizeM1BitWidth", res.SizeM1BitWidth);
}
};

30
lib/Transforms/IPO/LowerTypeTests.cpp
View File

@ -270,12 +270,12 @@ class LowerTypeTestsModule {
/// relative to the start address.
Constant *AlignLog2;
/// ByteArray, Inline, AllOnes: size of the memory region covering members
/// of this type identifier as a multiple of 2^AlignLog2.
Constant *Size;
/// ByteArray, Inline, AllOnes: one less than the size of the memory region
/// covering members of this type identifier as a multiple of 2^AlignLog2.
Constant *SizeM1;
/// ByteArray, Inline, AllOnes: range of the size expressed as a bit width.
unsigned SizeBitWidth;
/// ByteArray, Inline, AllOnes: range of SizeM1 expressed as a bit width.
unsigned SizeM1BitWidth;
/// ByteArray: the byte array to test the address against.
Constant *TheByteArray;
@ -593,8 +593,8 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
IntPtrTy));
Value *BitOffset = B.CreateOr(OffsetSHR, OffsetSHL);
Constant *BitSizeConst = ConstantExpr::getZExt(TIL.Size, IntPtrTy);
Value *OffsetInRange = B.CreateICmpULT(BitOffset, BitSizeConst);
Constant *BitSizeConst = ConstantExpr::getZExt(TIL.SizeM1, IntPtrTy);
Value *OffsetInRange = B.CreateICmpULE(BitOffset, BitSizeConst);
// If the bit set is all ones, testing against it is unnecessary.
if (TIL.TheKind == TypeTestResolution::AllOnes)
@ -711,13 +711,13 @@ void LowerTypeTestsModule::lowerTypeTestCalls(
if (BSI.isAllOnes()) {
TIL.TheKind = (BSI.BitSize == 1) ? TypeTestResolution::Single
: TypeTestResolution::AllOnes;
TIL.SizeBitWidth = (BSI.BitSize < 256) ? 8 : 32;
TIL.Size =
ConstantInt::get((BSI.BitSize < 256) ? Int8Ty : Int32Ty, BSI.BitSize);
TIL.SizeM1BitWidth = (BSI.BitSize <= 128) ? 7 : 32;
TIL.SizeM1 = ConstantInt::get((BSI.BitSize <= 128) ? Int8Ty : Int32Ty,
BSI.BitSize - 1);
} else if (BSI.BitSize <= 64) {
TIL.TheKind = TypeTestResolution::Inline;
TIL.SizeBitWidth = (BSI.BitSize <= 32) ? 5 : 6;
TIL.Size = ConstantInt::get(Int8Ty, BSI.BitSize);
TIL.SizeM1BitWidth = (BSI.BitSize <= 32) ? 5 : 6;
TIL.SizeM1 = ConstantInt::get(Int8Ty, BSI.BitSize - 1);
uint64_t InlineBits = 0;
for (auto Bit : BSI.Bits)
InlineBits |= uint64_t(1) << Bit;
@ -728,9 +728,9 @@ void LowerTypeTestsModule::lowerTypeTestCalls(
(BSI.BitSize <= 32) ? Int32Ty : Int64Ty, InlineBits);
} else {
TIL.TheKind = TypeTestResolution::ByteArray;
TIL.SizeBitWidth = (BSI.BitSize < 256) ? 8 : 32;
TIL.Size =
ConstantInt::get((BSI.BitSize < 256) ? Int8Ty : Int32Ty, BSI.BitSize);
TIL.SizeM1BitWidth = (BSI.BitSize <= 128) ? 7 : 32;
TIL.SizeM1 = ConstantInt::get((BSI.BitSize <= 128) ? Int8Ty : Int32Ty,
BSI.BitSize - 1);
++NumByteArraysCreated;
ByteArrayInfo *BAI = createByteArray(BSI);
TIL.TheByteArray = BAI->ByteArray;

2
test/Transforms/LowerTypeTests/Inputs/import-unsat.yaml
View File

@ -6,5 +6,5 @@ TypeIdMap:
typeid1:
TTRes:
Kind: Unsat
SizeBitWidth: 0
SizeM1BitWidth: 0
...

2
test/Transforms/LowerTypeTests/function.ll
View File

@ -43,7 +43,7 @@ declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone
define i1 @foo(i8* %p) {
; NATIVE: sub i64 {{.*}}, ptrtoint (void ()* @[[JT]] to i64)
; WASM32: sub i64 {{.*}}, ptrtoint (i8* getelementptr (i8, i8* null, i64 1) to i64)
; WASM32: icmp ult i64 {{.*}}, 2
; WASM32: icmp ule i64 {{.*}}, 1
%x = call i1 @llvm.type.test(i8* %p, metadata !"typeid1")
ret i1 %x
}

2
test/Transforms/LowerTypeTests/import-unsat.ll
View File

@ -10,7 +10,7 @@
; SUMMARY-NEXT: typeid1:
; SUMMARY-NEXT: TTRes:
; SUMMARY-NEXT: Kind: Unsat
; SUMMARY-NEXT: SizeBitWidth: 0
; SUMMARY-NEXT: SizeM1BitWidth: 0
target datalayout = "e-p:32:32"

6
test/Transforms/LowerTypeTests/simple.ll
View File

@ -69,7 +69,7 @@ define i1 @foo(i32* %p) {
; CHECK: [[R3:%[^ ]*]] = lshr i32 [[R2]], 2
; CHECK: [[R4:%[^ ]*]] = shl i32 [[R2]], 30
; CHECK: [[R5:%[^ ]*]] = or i32 [[R3]], [[R4]]
; CHECK: [[R6:%[^ ]*]] = icmp ult i32 [[R5]], 68
; CHECK: [[R6:%[^ ]*]] = icmp ule i32 [[R5]], 67
; CHECK: br i1 [[R6]]
; CHECK: [[R8:%[^ ]*]] = getelementptr i8, i8* @bits_use.{{[0-9]*}}, i32 [[R5]]
@ -96,7 +96,7 @@ define i1 @bar(i32* %p) {
; CHECK: [[S3:%[^ ]*]] = lshr i32 [[S2]], 8
; CHECK: [[S4:%[^ ]*]] = shl i32 [[S2]], 24
; CHECK: [[S5:%[^ ]*]] = or i32 [[S3]], [[S4]]
; CHECK: [[S6:%[^ ]*]] = icmp ult i32 [[S5]], 2
; CHECK: [[S6:%[^ ]*]] = icmp ule i32 [[S5]], 1
%x = call i1 @llvm.type.test(i8* %pi8, metadata !"typeid2")
; CHECK: ret i1 [[S6]]
@ -112,7 +112,7 @@ define i1 @baz(i32* %p) {
; CHECK: [[T3:%[^ ]*]] = lshr i32 [[T2]], 2
; CHECK: [[T4:%[^ ]*]] = shl i32 [[T2]], 30
; CHECK: [[T5:%[^ ]*]] = or i32 [[T3]], [[T4]]
; CHECK: [[T6:%[^ ]*]] = icmp ult i32 [[T5]], 66
; CHECK: [[T6:%[^ ]*]] = icmp ule i32 [[T5]], 65
; CHECK: br i1 [[T6]]
; CHECK: [[T8:%[^ ]*]] = getelementptr i8, i8* @bits_use{{(\.[0-9]*)?}}, i32 [[T5]]