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[PowerPC] Implement Vector Shift Builtins

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This patch implements the builtins for the vector shifts (shl, srl, sra), and
adds the appropriate test cases for these builtins. The builtins utilize the
vector shift instructions introduced within ISA 3.1.

Differential Revision: https://reviews.llvm.org/D83338
This commit is contained in:
Albion Fung 2020-08-12 18:26:43 -05:00
parent 3cea08454d
commit 3972d9461d
3 changed files with 89 additions and 0 deletions
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3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1128,6 +1128,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
if (Subtarget.has64BitSupport())
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
if (Subtarget.isISA3_1())
setOperationAction(ISD::SRA, MVT::v1i128, Legal);
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
if (!isPPC64) {

12
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -1288,6 +1288,18 @@ let Predicates = [IsISA3_1] in {
(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
}
let AddedComplexity = 400, Predicates = [IsISA3_1] in {

74
test/CodeGen/PowerPC/p10-vector-shift.ll Normal file
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@ -0,0 +1,74 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; These test cases demonstrate that the vector shift quadword instructions
; introduced within Power10 are correctly exploited.
define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vslq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vslq v2, v2, v3
; CHECK-NEXT: blr
entry:
%rem = urem <1 x i128> %b, <i128 128>
%shl = shl <1 x i128> %a, %rem
ret <1 x i128> %shl
}
define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vsrq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsrq v2, v2, v3
; CHECK-NEXT: blr
entry:
%rem = urem <1 x i128> %b, <i128 128>
%shr = lshr <1 x i128> %a, %rem
ret <1 x i128> %shr
}
define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vsraq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsraq v2, v2, v3
; CHECK-NEXT: blr
entry:
%rem = urem <1 x i128> %b, <i128 128>
%shr = ashr <1 x i128> %a, %rem
ret <1 x i128> %shr
}
define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vslq2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vslq v2, v2, v3
; CHECK-NEXT: blr
entry:
%shl = shl <1 x i128> %a, %b
ret <1 x i128> %shl
}
define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vsrq2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsrq v2, v2, v3
; CHECK-NEXT: blr
entry:
%shr = lshr <1 x i128> %a, %b
ret <1 x i128> %shr
}
define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
; CHECK-LABEL: test_vec_vsraq2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsraq v2, v2, v3
; CHECK-NEXT: blr
entry:
%shr = ashr <1 x i128> %a, %b
ret <1 x i128> %shr
}