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Make LowerCallTo and LowerArguments take a DebugLoc

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argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
This commit is contained in:
Dale Johannesen 2009-01-30 23:10:59 +00:00
parent cebc5ac36d
commit 39738b1ff8
17 changed files with 83 additions and 53 deletions
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5
include/llvm/Target/TargetLowering.h
View File

@ -29,6 +29,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Codegen/DebugLoc.h"
#include <climits>
#include <map>
#include <vector>
@ -1059,7 +1060,7 @@ public:
/// lower the arguments for the specified function, into the specified DAG.
virtual void
LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue>& ArgValues);
SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call. This returns a pair of operands. The first element is the
@ -1084,7 +1085,7 @@ public:
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned CallingConv,
bool isTailCall, SDValue Callee, ArgListTy &Args,
SelectionDAG &DAG);
SelectionDAG &DAG, DebugLoc dl);
/// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
/// memcpy. This can be used by targets to provide code sequences for cases

6
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -991,6 +991,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
assert(isTypeLegal(Op.getValueType()) &&
"Caller should expand or promote operands that are not legal!");
SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc();
// If this operation defines any values that cannot be represented in a
// register on this target, make sure to expand or promote them.
@ -4323,7 +4324,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
TLI.LowerCallTo(Tmp1, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
DAG.getExternalSymbol("abort", TLI.getPointerTy()),
Args, DAG);
Args, DAG, dl);
Result = CallResult.second;
break;
}
@ -5791,7 +5792,8 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
const Type *RetTy = Node->getValueType(0).getTypeForMVT();
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
CallingConv::C, false, Callee, Args, DAG);
CallingConv::C, false, Callee, Args, DAG,
Node->getDebugLoc());
// Legalize the call sequence, starting with the chain. This will advance
// the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that

4
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -987,9 +987,11 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
TLI.getPointerTy());
const Type *RetTy = RetVT.getTypeForMVT();
// FIXME pass in debug loc
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, CallingConv::C, false, Callee, Args, DAG);
false, CallingConv::C, false, Callee, Args, DAG,
DebugLoc::getUnknownLoc());
return CallInfo.first;
}

9
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -3285,11 +3285,12 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, SDValue Dst,
Entry.Node = Dst; Args.push_back(Entry);
Entry.Node = Src; Args.push_back(Entry);
Entry.Node = Size; Args.push_back(Entry);
// FIXME: pass in DebugLoc
std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memcpy", TLI.getPointerTy()),
Args, *this);
Args, *this, DebugLoc::getUnknownLoc());
return CallResult.second;
}
@ -3330,11 +3331,12 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, SDValue Dst,
Entry.Node = Dst; Args.push_back(Entry);
Entry.Node = Src; Args.push_back(Entry);
Entry.Node = Size; Args.push_back(Entry);
// FIXME: pass in DebugLoc
std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memmove", TLI.getPointerTy()),
Args, *this);
Args, *this, DebugLoc::getUnknownLoc());
return CallResult.second;
}
@ -3381,11 +3383,12 @@ SDValue SelectionDAG::getMemset(SDValue Chain, SDValue Dst,
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
Args.push_back(Entry);
// FIXME: pass in DebugLoc
std::pair<SDValue,SDValue> CallResult =
TLI.LowerCallTo(Chain, Type::VoidTy,
false, false, false, false, CallingConv::C, false,
getExternalSymbol("memset", TLI.getPointerTy()),
Args, *this);
Args, *this, DebugLoc::getUnknownLoc());
return CallResult.second;
}

20
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -4344,7 +4344,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
CS.paramHasAttr(0, Attribute::InReg),
CS.getCallingConv(),
IsTailCall && PerformTailCallOpt,
Callee, Args, DAG);
Callee, Args, DAG, DAG.getCurDebugLoc());
if (CS.getType() != Type::VoidTy)
setValue(CS.getInstruction(), Result.first);
DAG.setRoot(Result.second);
@ -5357,7 +5357,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
CallingConv::C, PerformTailCallOpt,
DAG.getExternalSymbol("malloc", IntPtr),
Args, DAG);
Args, DAG, DAG.getCurDebugLoc());
setValue(&I, Result.first); // Pointers always fit in registers
DAG.setRoot(Result.second);
}
@ -5372,7 +5372,8 @@ void SelectionDAGLowering::visitFree(FreeInst &I) {
std::pair<SDValue,SDValue> Result =
TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
CallingConv::C, PerformTailCallOpt,
DAG.getExternalSymbol("free", IntPtr), Args, DAG);
DAG.getExternalSymbol("free", IntPtr), Args, DAG,
DAG.getCurDebugLoc());
DAG.setRoot(Result.second);
}
@ -5412,7 +5413,8 @@ void SelectionDAGLowering::visitVACopy(CallInst &I) {
/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
/// integrated into SDISel.
void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &ArgValues) {
SmallVectorImpl<SDValue> &ArgValues,
DebugLoc dl) {
// Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
SmallVector<SDValue, 3+16> Ops;
Ops.push_back(DAG.getRoot());
@ -5477,7 +5479,7 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
RetVals.push_back(MVT::Other);
// Create the node.
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, DAG.getCurDebugLoc(),
SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
DAG.getVTList(&RetVals[0], RetVals.size()),
&Ops[0], Ops.size()).getNode();
@ -5545,7 +5547,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool isInreg,
unsigned CallingConv, bool isTailCall,
SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
assert((!isTailCall || PerformTailCallOpt) &&
"isTailCall set when tail-call optimizations are disabled!");
@ -5636,7 +5638,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
LoweredRetTys.push_back(MVT::Other); // Always has a chain.
// Create the CALL node.
SDValue Res = DAG.getCall(CallingConv, DAG.getCurDebugLoc(),
SDValue Res = DAG.getCall(CallingConv, dl,
isVarArg, isTailCall, isInreg,
DAG.getVTList(&LoweredRetTys[0],
LoweredRetTys.size()),
@ -5668,7 +5670,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
AssertOp);
ReturnValues.push_back(ReturnValue);
}
Res = DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(),
Res = DAG.getNode(ISD::MERGE_VALUES, dl,
DAG.getVTList(&RetTys[0], RetTys.size()),
&ReturnValues[0], ReturnValues.size());
}
@ -5712,7 +5714,7 @@ LowerArguments(BasicBlock *LLVMBB) {
Function &F = *LLVMBB->getParent();
SDValue OldRoot = SDL->DAG.getRoot();
SmallVector<SDValue, 16> Args;
TLI.LowerArguments(F, SDL->DAG, Args);
TLI.LowerArguments(F, SDL->DAG, Args, SDL->DAG.getCurDebugLoc());
unsigned a = 0;
for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();

4
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -740,10 +740,12 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Entry.Node = Argument;
Entry.Ty = (const Type *) Type::Int32Ty;
Args.push_back(Entry);
// FIXME: is there useful debug info available here?
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
CallingConv::C, false,
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
DebugLoc::getUnknownLoc());
return CallResult.first;
}

18
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -356,7 +356,8 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned CallingConv,
bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl) {
int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
@ -374,11 +375,13 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
// Promote the integer to 64 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (Args[i].isSExt)
Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
MVT::i64, Args[i].Node);
else if (Args[i].isZExt)
Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
MVT::i64, Args[i].Node);
else
Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
break;
case MVT::i64:
case MVT::f64:
@ -402,7 +405,8 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
DAG.getIntPtrConstant(0, true), SDValue());
@ -416,10 +420,10 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
AssertKind = ISD::AssertZext;
if (AssertKind != ISD::DELETED_NODE)
RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
DAG.getValueType(RetTyVT));
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
}
return std::make_pair(RetVal, Chain);

3
lib/Target/Alpha/AlphaISelLowering.h
View File

@ -87,7 +87,8 @@ namespace llvm {
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned CC, bool isTailCall,
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl);
ConstraintType getConstraintType(const std::string &Constraint) const;

3
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -113,7 +113,8 @@ namespace {
const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT();
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
CallingConv::C, false, Callee, Args, DAG);
CallingConv::C, false, Callee, Args, DAG,
Op.getNode()->getDebugLoc());
return CallInfo.first;
}

36
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -145,7 +145,8 @@ MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
}
void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &ArgValues) {
SmallVectorImpl<SDValue> &ArgValues,
DebugLoc dl) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
@ -199,7 +200,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
MVT::f64);
if (I->getType() == Type::FloatTy)
argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
DAG.getIntPtrConstant(0));
break;
case MVT::i1: // NOTE: as far as C abi stuff goes,
@ -218,7 +219,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
argt = newroot =
DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
if ( getValueType(I->getType()) != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
newroot);
break;
}
@ -230,7 +231,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()),
argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
DAG.getEntryNode(), FIN, NULL, 0);
}
++count;
@ -307,7 +308,8 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned CallingConv,
bool isTailCall, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG) {
ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
@ -360,7 +362,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
ExtendKind = ISD::SIGN_EXTEND;
else if (Args[i].isZExt)
ExtendKind = ISD::ZERO_EXTEND;
Val = DAG.getNode(ExtendKind, MVT::i64, Val);
Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
// XXX: fall through
}
case MVT::i64:
@ -373,7 +375,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
break;
case MVT::f32:
//promote to 64-bits
Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
// XXX: fall through
case MVT::f64:
if(RegValuesToPass.size() >= 8) {
@ -392,19 +394,21 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
}
SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
}
if(ValToConvert.getNode()) {
Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
MVT::i64, ValToConvert));
}
}
// Emit all stores, make sure they occur before any copies into physregs.
if (!Stores.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
Chain = DAG.getNode(ISD::TokenFactor, dl,
MVT::Other, &Stores[0],Stores.size());
static const unsigned IntArgRegs[] = {
IA64::out0, IA64::out1, IA64::out2, IA64::out3,
@ -477,7 +481,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
assert(0 && "this should never happen!\n");
// to make way for a hack:
Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
&CallOperands[0], CallOperands.size());
InFlag = Chain.getValue(1);
@ -508,7 +512,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
break;
}
case MVT::i8:
@ -520,9 +524,9 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
// keep track of whether it is sign or zero extended (todo: bools?)
/* XXX
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
MVT::i64, RetVal, DAG.getValueType(RetTyVT));
dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
*/
RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
break;
case MVT::i64:
RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
@ -532,7 +536,7 @@ IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
case MVT::f32:
RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal,
RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
DAG.getIntPtrConstant(0));
break;
case MVT::f64:

6
lib/Target/IA64/IA64ISelLowering.h
View File

@ -54,7 +54,8 @@ namespace llvm {
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &ArgValues);
SmallVectorImpl<SDValue> &ArgValues,
DebugLoc dl);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
@ -62,7 +63,8 @@ namespace llvm {
LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg,
unsigned CC, bool isTailCall,
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
SDValue Callee, ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl);
/// LowerOperation - for custom lowering specific ops
/// (currently, only "ret void")

7
lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -172,7 +172,7 @@ SDValue
PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
MVT RetVT, const SDValue *Ops,
unsigned NumOps, bool isSigned,
SelectionDAG &DAG) {
SelectionDAG &DAG, DebugLoc dl) {
TargetLowering::ArgListTy Args;
Args.reserve(NumOps);
@ -190,7 +190,7 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
const Type *RetTy = RetVT.getTypeForMVT();
std::pair<SDValue,SDValue> CallInfo =
LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, CallingConv::C, false, Callee, Args, DAG);
false, CallingConv::C, false, Callee, Args, DAG, dl);
return CallInfo.first;
}
@ -758,7 +758,8 @@ SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
SmallVector<SDValue, 2> Ops(2);
Ops[0] = Value;
Ops[1] = Amt;
SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2, true, DAG);
SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
true, DAG, N->getDebugLoc());
return Call;
}

2
lib/Target/PIC16/PIC16ISelLowering.h
View File

@ -168,7 +168,7 @@ namespace llvm {
// Make PIC16 Libcall
SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned,
SelectionDAG &DAG);
SelectionDAG &DAG, DebugLoc dl);
// Check if operation has a direct load operand.
inline bool isDirectLoad(const SDValue Op);

3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1229,6 +1229,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
DebugLoc dl = Op.getNode()->getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = (PtrVT == MVT::i64);
@ -1254,7 +1255,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
false, false, CallingConv::C, false,
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
Args, DAG);
Args, DAG, dl);
SDValue Ops[] =
{ CallResult.first, CallResult.second };

3
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -77,7 +77,8 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
/// in FP registers for fastcc functions.
void
SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &ArgValues) {
SmallVectorImpl<SDValue> &ArgValues,
DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();

3
lib/Target/Sparc/SparcISelLowering.h
View File

@ -58,7 +58,8 @@ namespace llvm {
unsigned Depth = 0) const;
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &ArgValues);
SmallVectorImpl<SDValue> &ArgValues,
DebugLoc dl);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -5532,10 +5532,12 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
Args.push_back(Entry);
Entry.Node = Size;
Args.push_back(Entry);
// FIXME provide DebugLoc info
std::pair<SDValue,SDValue> CallResult =
LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
CallingConv::C, false,
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG,
DebugLoc::getUnknownLoc());
return CallResult.second;
}