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AMDGPU: Introduce a flag to disable mul24 intrinsic formation
llvm-svn: 369856
This commit is contained in:
Matt Arsenault
parent
1e58b1c1f6
commit
397e3680de
@ -55,6 +55,12 @@ static cl::opt<bool> WidenLoads(
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cl::ReallyHidden,
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cl::init(true));
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static cl::opt<bool> UseMul24Intrin(
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"amdgpu-codegenprepare-mul24",
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cl::desc("Introduce mul24 intrinsics in AMDGPUCodeGenPrepare"),
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cl::ReallyHidden,
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cl::init(true));
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class AMDGPUCodeGenPrepare : public FunctionPass,
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public InstVisitor<AMDGPUCodeGenPrepare, bool> {
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const GCNSubtarget *ST = nullptr;
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@ -879,7 +885,7 @@ bool AMDGPUCodeGenPrepare::visitBinaryOperator(BinaryOperator &I) {
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DA->isUniform(&I) && promoteUniformOpToI32(I))
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return true;
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if (replaceMulWithMul24(I))
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if (UseMul24Intrin && replaceMulWithMul24(I))
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return true;
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bool Changed = false;
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@ -1,18 +1,23 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck -check-prefix=SI %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare %s | FileCheck -check-prefix=VI %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=fiji -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare %s | FileCheck -check-prefix=DISABLED %s
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define i16 @mul_i16(i16 %lhs, i16 %rhs) {
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; SI-LABEL: @mul_i16(
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; SI-NEXT: [[TMP1:%.*]] = zext i16 [[LHS:%.*]] to i32
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; SI-NEXT: [[TMP2:%.*]] = zext i16 [[RHS:%.*]] to i32
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; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
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; SI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16
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; SI-NEXT: ret i16 [[TMP4]]
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; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i16
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; SI-NEXT: ret i16 [[MUL]]
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;
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; VI-LABEL: @mul_i16(
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; VI-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
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; VI-NEXT: ret i16 [[MUL]]
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;
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; DISABLED-LABEL: @mul_i16(
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; DISABLED-NEXT: [[MUL:%.*]] = mul i16 [[LHS:%.*]], [[RHS:%.*]]
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; DISABLED-NEXT: ret i16 [[MUL]]
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;
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%mul = mul i16 %lhs, %rhs
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ret i16 %mul
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@ -24,16 +29,24 @@ define i32 @smul24_i32(i32 %lhs, i32 %rhs) {
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; SI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
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; SI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
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; SI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8
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; SI-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
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; SI-NEXT: ret i32 [[TMP1]]
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; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
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; SI-NEXT: ret i32 [[MUL]]
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;
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; VI-LABEL: @smul24_i32(
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; VI-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
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; VI-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
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; VI-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
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; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8
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; VI-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
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; VI-NEXT: ret i32 [[TMP1]]
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; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[LHS24]], i32 [[RHS24]])
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; VI-NEXT: ret i32 [[MUL]]
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;
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; DISABLED-LABEL: @smul24_i32(
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; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 8
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; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 8
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; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 8
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; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 8
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; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret i32 [[MUL]]
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;
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%shl.lhs = shl i32 %lhs, 8
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%lhs24 = ashr i32 %shl.lhs, 8
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@ -56,8 +69,8 @@ define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]])
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; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]])
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; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
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; SI-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; SI-NEXT: ret <2 x i32> [[TMP8]]
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; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; SI-NEXT: ret <2 x i32> [[MUL]]
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;
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; VI-LABEL: @smul24_v2i32(
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; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
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@ -71,8 +84,16 @@ define <2 x i32> @smul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP3]])
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; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP2]], i32 [[TMP4]])
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; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
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; VI-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; VI-NEXT: ret <2 x i32> [[TMP8]]
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; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; VI-NEXT: ret <2 x i32> [[MUL]]
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;
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; DISABLED-LABEL: @smul24_v2i32(
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; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i32> [[LHS:%.*]], <i32 8, i32 8>
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; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i32> [[SHL_LHS]], <i32 8, i32 8>
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; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i32> [[RHS:%.*]], <i32 8, i32 8>
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; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i32> [[LHS]], <i32 8, i32 8>
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; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret <2 x i32> [[MUL]]
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;
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%shl.lhs = shl <2 x i32> %lhs, <i32 8, i32 8>
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%lhs24 = ashr <2 x i32> %shl.lhs, <i32 8, i32 8>
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@ -86,14 +107,20 @@ define i32 @umul24_i32(i32 %lhs, i32 %rhs) {
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; SI-LABEL: @umul24_i32(
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; SI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
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; SI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
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; SI-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
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; SI-NEXT: ret i32 [[TMP1]]
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; SI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
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; SI-NEXT: ret i32 [[MUL]]
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;
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; VI-LABEL: @umul24_i32(
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; VI-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
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; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
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; VI-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
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; VI-NEXT: ret i32 [[TMP1]]
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; VI-NEXT: [[MUL:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[LHS24]], i32 [[RHS24]])
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; VI-NEXT: ret i32 [[MUL]]
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;
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; DISABLED-LABEL: @umul24_i32(
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; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 16777215
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; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 16777215
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; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret i32 [[MUL]]
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;
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%lhs24 = and i32 %lhs, 16777215
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%rhs24 = and i32 %rhs, 16777215
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@ -112,8 +139,8 @@ define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; SI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]])
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; SI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]])
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; SI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
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; SI-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; SI-NEXT: ret <2 x i32> [[TMP8]]
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; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; SI-NEXT: ret <2 x i32> [[MUL]]
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;
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; VI-LABEL: @umul24_v2i32(
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; VI-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
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@ -125,8 +152,14 @@ define <2 x i32> @umul24_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; VI-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP3]])
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; VI-NEXT: [[TMP6:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP2]], i32 [[TMP4]])
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; VI-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> undef, i32 [[TMP5]], i64 0
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; VI-NEXT: [[TMP8:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; VI-NEXT: ret <2 x i32> [[TMP8]]
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; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i32> [[TMP7]], i32 [[TMP6]], i64 1
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; VI-NEXT: ret <2 x i32> [[MUL]]
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;
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; DISABLED-LABEL: @umul24_v2i32(
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; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i32> [[LHS:%.*]], <i32 16777215, i32 16777215>
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; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i32> [[RHS:%.*]], <i32 16777215, i32 16777215>
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; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i32> [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret <2 x i32> [[MUL]]
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;
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%lhs24 = and <2 x i32> %lhs, <i32 16777215, i32 16777215>
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%rhs24 = and <2 x i32> %rhs, <i32 16777215, i32 16777215>
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@ -143,8 +176,8 @@ define i64 @smul24_i64(i64 %lhs, i64 %rhs) {
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; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
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; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
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; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
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; SI-NEXT: [[TMP4:%.*]] = sext i32 [[TMP3]] to i64
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; SI-NEXT: ret i64 [[TMP4]]
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; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
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; SI-NEXT: ret i64 [[MUL]]
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;
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; VI-LABEL: @smul24_i64(
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; VI-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
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@ -154,8 +187,16 @@ define i64 @smul24_i64(i64 %lhs, i64 %rhs) {
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; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
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; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
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; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
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; VI-NEXT: [[TMP4:%.*]] = sext i32 [[TMP3]] to i64
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; VI-NEXT: ret i64 [[TMP4]]
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; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i64
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; VI-NEXT: ret i64 [[MUL]]
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;
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; DISABLED-LABEL: @smul24_i64(
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; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i64 [[LHS:%.*]], 40
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; DISABLED-NEXT: [[LHS24:%.*]] = ashr i64 [[SHL_LHS]], 40
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; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i64 [[RHS:%.*]], 40
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; DISABLED-NEXT: [[RHS24:%.*]] = ashr i64 [[LHS]], 40
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; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret i64 [[MUL]]
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;
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%shl.lhs = shl i64 %lhs, 40
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%lhs24 = ashr i64 %shl.lhs, 40
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@ -172,8 +213,8 @@ define i64 @umul24_i64(i64 %lhs, i64 %rhs) {
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; SI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
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; SI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
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; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
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; SI-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; SI-NEXT: ret i64 [[TMP4]]
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; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
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; SI-NEXT: ret i64 [[MUL]]
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;
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; VI-LABEL: @umul24_i64(
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; VI-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
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@ -181,8 +222,14 @@ define i64 @umul24_i64(i64 %lhs, i64 %rhs) {
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; VI-NEXT: [[TMP1:%.*]] = trunc i64 [[LHS24]] to i32
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; VI-NEXT: [[TMP2:%.*]] = trunc i64 [[RHS24]] to i32
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; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
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; VI-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; VI-NEXT: ret i64 [[TMP4]]
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; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i64
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; VI-NEXT: ret i64 [[MUL]]
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;
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; DISABLED-LABEL: @umul24_i64(
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; DISABLED-NEXT: [[LHS24:%.*]] = and i64 [[LHS:%.*]], 16777215
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; DISABLED-NEXT: [[RHS24:%.*]] = and i64 [[RHS:%.*]], 16777215
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; DISABLED-NEXT: [[MUL:%.*]] = mul i64 [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret i64 [[MUL]]
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;
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%lhs24 = and i64 %lhs, 16777215
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%rhs24 = and i64 %rhs, 16777215
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@ -199,8 +246,8 @@ define i31 @smul24_i31(i31 %lhs, i31 %rhs) {
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; SI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32
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; SI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32
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; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
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; SI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i31
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; SI-NEXT: ret i31 [[TMP4]]
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; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
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; SI-NEXT: ret i31 [[MUL]]
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;
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; VI-LABEL: @smul24_i31(
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; VI-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
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@ -210,8 +257,16 @@ define i31 @smul24_i31(i31 %lhs, i31 %rhs) {
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; VI-NEXT: [[TMP1:%.*]] = sext i31 [[LHS24]] to i32
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; VI-NEXT: [[TMP2:%.*]] = sext i31 [[RHS24]] to i32
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; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
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; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i31
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; VI-NEXT: ret i31 [[TMP4]]
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; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
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; VI-NEXT: ret i31 [[MUL]]
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;
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; DISABLED-LABEL: @smul24_i31(
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; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i31 [[LHS:%.*]], 7
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; DISABLED-NEXT: [[LHS24:%.*]] = ashr i31 [[SHL_LHS]], 7
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; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i31 [[RHS:%.*]], 7
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; DISABLED-NEXT: [[RHS24:%.*]] = ashr i31 [[LHS]], 7
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; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
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; DISABLED-NEXT: ret i31 [[MUL]]
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;
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%shl.lhs = shl i31 %lhs, 7
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%lhs24 = ashr i31 %shl.lhs, 7
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@ -228,8 +283,8 @@ define i31 @umul24_i31(i31 %lhs, i31 %rhs) {
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; SI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32
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; SI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32
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; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
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; SI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i31
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; SI-NEXT: ret i31 [[TMP4]]
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; SI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
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; SI-NEXT: ret i31 [[MUL]]
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;
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; VI-LABEL: @umul24_i31(
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; VI-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
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@ -237,8 +292,14 @@ define i31 @umul24_i31(i31 %lhs, i31 %rhs) {
|
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; VI-NEXT: [[TMP1:%.*]] = zext i31 [[LHS24]] to i32
|
||||
; VI-NEXT: [[TMP2:%.*]] = zext i31 [[RHS24]] to i32
|
||||
; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
|
||||
; VI-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i31
|
||||
; VI-NEXT: ret i31 [[TMP4]]
|
||||
; VI-NEXT: [[MUL:%.*]] = trunc i32 [[TMP3]] to i31
|
||||
; VI-NEXT: ret i31 [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @umul24_i31(
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = and i31 [[LHS:%.*]], 16777215
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = and i31 [[RHS:%.*]], 16777215
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul i31 [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret i31 [[MUL]]
|
||||
;
|
||||
%lhs24 = and i31 %lhs, 16777215
|
||||
%rhs24 = and i31 %rhs, 16777215
|
||||
@ -263,8 +324,8 @@ define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
|
||||
; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
|
||||
; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
|
||||
; SI-NEXT: [[TMP14:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i31> [[TMP14]]
|
||||
; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
; VI-LABEL: @umul24_v2i31(
|
||||
; VI-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
|
||||
@ -282,8 +343,14 @@ define <2 x i31> @umul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
|
||||
; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
|
||||
; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
|
||||
; VI-NEXT: [[TMP14:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i31> [[TMP14]]
|
||||
; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @umul24_v2i31(
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = and <2 x i31> [[LHS:%.*]], <i31 16777215, i31 16777215>
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = and <2 x i31> [[RHS:%.*]], <i31 16777215, i31 16777215>
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
%lhs24 = and <2 x i31> %lhs, <i31 16777215, i31 16777215>
|
||||
%rhs24 = and <2 x i31> %rhs, <i31 16777215, i31 16777215>
|
||||
@ -310,8 +377,8 @@ define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
|
||||
; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; SI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
|
||||
; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
|
||||
; SI-NEXT: [[TMP14:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i31> [[TMP14]]
|
||||
; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
; VI-LABEL: @smul24_v2i31(
|
||||
; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
|
||||
@ -331,8 +398,16 @@ define <2 x i31> @smul24_v2i31(<2 x i31> %lhs, <2 x i31> %rhs) {
|
||||
; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; VI-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i31
|
||||
; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i31> undef, i31 [[TMP8]], i64 0
|
||||
; VI-NEXT: [[TMP14:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i31> [[TMP14]]
|
||||
; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i31> [[TMP13]], i31 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @smul24_v2i31(
|
||||
; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i31> [[LHS:%.*]], <i31 8, i31 8>
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i31> [[SHL_LHS]], <i31 8, i31 8>
|
||||
; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i31> [[RHS:%.*]], <i31 8, i31 8>
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i31> [[LHS]], <i31 8, i31 8>
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i31> [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret <2 x i31> [[MUL]]
|
||||
;
|
||||
%shl.lhs = shl <2 x i31> %lhs, <i31 8, i31 8>
|
||||
%lhs24 = ashr <2 x i31> %shl.lhs, <i31 8, i31 8>
|
||||
@ -351,8 +426,8 @@ define i33 @smul24_i33(i33 %lhs, i33 %rhs) {
|
||||
; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
|
||||
; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
|
||||
; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
|
||||
; SI-NEXT: [[TMP4:%.*]] = sext i32 [[TMP3]] to i33
|
||||
; SI-NEXT: ret i33 [[TMP4]]
|
||||
; SI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33
|
||||
; SI-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
; VI-LABEL: @smul24_i33(
|
||||
; VI-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
|
||||
@ -362,8 +437,16 @@ define i33 @smul24_i33(i33 %lhs, i33 %rhs) {
|
||||
; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
|
||||
; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
|
||||
; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP1]], i32 [[TMP2]])
|
||||
; VI-NEXT: [[TMP4:%.*]] = sext i32 [[TMP3]] to i33
|
||||
; VI-NEXT: ret i33 [[TMP4]]
|
||||
; VI-NEXT: [[MUL:%.*]] = sext i32 [[TMP3]] to i33
|
||||
; VI-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @smul24_i33(
|
||||
; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i33 [[LHS:%.*]], 9
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = ashr i33 [[SHL_LHS]], 9
|
||||
; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i33 [[RHS:%.*]], 9
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = ashr i33 [[LHS]], 9
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
%shl.lhs = shl i33 %lhs, 9
|
||||
%lhs24 = ashr i33 %shl.lhs, 9
|
||||
@ -380,8 +463,8 @@ define i33 @umul24_i33(i33 %lhs, i33 %rhs) {
|
||||
; SI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
|
||||
; SI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
|
||||
; SI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
|
||||
; SI-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i33
|
||||
; SI-NEXT: ret i33 [[TMP4]]
|
||||
; SI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33
|
||||
; SI-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
; VI-LABEL: @umul24_i33(
|
||||
; VI-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
|
||||
@ -389,8 +472,14 @@ define i33 @umul24_i33(i33 %lhs, i33 %rhs) {
|
||||
; VI-NEXT: [[TMP1:%.*]] = trunc i33 [[LHS24]] to i32
|
||||
; VI-NEXT: [[TMP2:%.*]] = trunc i33 [[RHS24]] to i32
|
||||
; VI-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.mul.u24(i32 [[TMP1]], i32 [[TMP2]])
|
||||
; VI-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i33
|
||||
; VI-NEXT: ret i33 [[TMP4]]
|
||||
; VI-NEXT: [[MUL:%.*]] = zext i32 [[TMP3]] to i33
|
||||
; VI-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @umul24_i33(
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = and i33 [[LHS:%.*]], 16777215
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = and i33 [[RHS:%.*]], 16777215
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul i33 [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret i33 [[MUL]]
|
||||
;
|
||||
%lhs24 = and i33 %lhs, 16777215
|
||||
%rhs24 = and i33 %rhs, 16777215
|
||||
@ -414,6 +503,14 @@ define i32 @smul25_i32(i32 %lhs, i32 %rhs) {
|
||||
; VI-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7
|
||||
; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
|
||||
; VI-NEXT: ret i32 [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @smul25_i32(
|
||||
; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl i32 [[LHS:%.*]], 7
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = ashr i32 [[SHL_LHS]], 7
|
||||
; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl i32 [[RHS:%.*]], 7
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = ashr i32 [[LHS]], 7
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret i32 [[MUL]]
|
||||
;
|
||||
%shl.lhs = shl i32 %lhs, 7
|
||||
%lhs24 = ashr i32 %shl.lhs, 7
|
||||
@ -435,6 +532,12 @@ define i32 @umul25_i32(i32 %lhs, i32 %rhs) {
|
||||
; VI-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
|
||||
; VI-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
|
||||
; VI-NEXT: ret i32 [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @umul25_i32(
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = and i32 [[LHS:%.*]], 33554431
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = and i32 [[RHS:%.*]], 33554431
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul i32 [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret i32 [[MUL]]
|
||||
;
|
||||
%lhs24 = and i32 %lhs, 33554431
|
||||
%rhs24 = and i32 %rhs, 33554431
|
||||
@ -461,8 +564,8 @@ define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) {
|
||||
; SI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; SI-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i33
|
||||
; SI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> undef, i33 [[TMP8]], i64 0
|
||||
; SI-NEXT: [[TMP14:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i33> [[TMP14]]
|
||||
; SI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
|
||||
; SI-NEXT: ret <2 x i33> [[MUL]]
|
||||
;
|
||||
; VI-LABEL: @smul24_v2i33(
|
||||
; VI-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
|
||||
@ -482,8 +585,16 @@ define <2 x i33> @smul24_v2i33(<2 x i33> %lhs, <2 x i33> %rhs) {
|
||||
; VI-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.mul.i24(i32 [[TMP9]], i32 [[TMP10]])
|
||||
; VI-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i33
|
||||
; VI-NEXT: [[TMP13:%.*]] = insertelement <2 x i33> undef, i33 [[TMP8]], i64 0
|
||||
; VI-NEXT: [[TMP14:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i33> [[TMP14]]
|
||||
; VI-NEXT: [[MUL:%.*]] = insertelement <2 x i33> [[TMP13]], i33 [[TMP12]], i64 1
|
||||
; VI-NEXT: ret <2 x i33> [[MUL]]
|
||||
;
|
||||
; DISABLED-LABEL: @smul24_v2i33(
|
||||
; DISABLED-NEXT: [[SHL_LHS:%.*]] = shl <2 x i33> [[LHS:%.*]], <i33 9, i33 9>
|
||||
; DISABLED-NEXT: [[LHS24:%.*]] = ashr <2 x i33> [[SHL_LHS]], <i33 9, i33 9>
|
||||
; DISABLED-NEXT: [[LSHR_RHS:%.*]] = shl <2 x i33> [[RHS:%.*]], <i33 9, i33 9>
|
||||
; DISABLED-NEXT: [[RHS24:%.*]] = ashr <2 x i33> [[LHS]], <i33 9, i33 9>
|
||||
; DISABLED-NEXT: [[MUL:%.*]] = mul <2 x i33> [[LHS24]], [[RHS24]]
|
||||
; DISABLED-NEXT: ret <2 x i33> [[MUL]]
|
||||
;
|
||||
%shl.lhs = shl <2 x i33> %lhs, <i33 9, i33 9>
|
||||
%lhs24 = ashr <2 x i33> %shl.lhs, <i33 9, i33 9>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user